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22. ACM Great Lakes Symposium on VLSI 2013: Paris, France
- José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse K. Coskun:
Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. ACM 2013, ISBN 978-1-4503-2032-0
Test 1
- Rashmi Moudgil, Dinesh Ganta, Leyla Nazhandali, Michael S. Hsiao, Chao Wang, T. Simin Hall:
A novel statistical and circuit-based technique for counterfeit detection in existing ICs. 1-6 - Cinzia Bernardeschi
, Luca Cassano
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs. 7-12 - Babak Saghaie, Roshan G. Ragel, Sri Parameswaran
A novel intermittent fault Markov model for deep sub-micron processors. 13-18 - Shun-Ming Syu, Yu-Hui Shao, Ing-Chao Lin:
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy. 19-24
Low power
- Yi Xiang, Sudeep Pasricha:
Harvesting-aware energy management for multicore platforms with hybrid energy storage. 25-30 - Krishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki J. Murakami:
Early stage power management for 3D FPGAs considering hierarchical routing resources. 31-36 - Pablo Royer, Marisa López-Vallejo
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node. 37-42 - Komal Jothi, Haitham Akkary:
Virtual register renaming: energy efficient substrate for continual flow pipelines. 43-48
Best paper session
- Can Sitik, Baris Taskin:
Skew-bounded low swing clock tree optimization. 49-54 - Mengjie Mao, Hai (Helen) Li
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. 55-60 - Qing Xie, Yanzhi Wang, Massoud Pedram:
Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above. 61-66
VLSI circuits
- Tzu-Yuan Kuo, Keng-Jui Chang, Jen-Hsiang Lee, Zong-Wu He, Jinn-Shyan Wang:
An energy-efficient truly all-digital temperature sensor for SoC applications. 67-70 - Hailang Wang, Mohammad H. Asgari, Emre Salman:
Efficient characterization of TSV-to-transistor noise coupling in 3D ICs. 71-76 - Muhammad E. S. Elrabaa:
A portable high-frequency digitally controlled oscillator (DCO). 77-82 - Jaeyoung Kim
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS. 83-88
CAD 1
- Aditya Belsare, Steve Liu, Sunil P. Khatri:
GPU implementation of a scalable non-linear congruential generator for cryptography applications. 89-94 - Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. 95-100 - Tun Li, Yang Guo, Wanwei Liu, Mingsheng Tang
Translation validation of scheduling in high level synthesis. 101-106 - Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen:
LASER: layout-aware analog synthesis environment on laker. 107-112
VLSI for biology
- Dimitris Koukounis, Christos Ttofis, Theocharis Theocharides
Hardware acceleration of retinal blood vasculature segmentation. 113-118 - Li-Lan Wang, Chia-Hsiang Yang
A 191μW BPSK demodulator for data and power telemetry in biomedical implants. 119-124 - David Watson, Ali Ahmadinia, Gordon Morison, Tom Buggy:
Custom memory architecture for multi-core implementation of face detection algorithm. 125-130
Emerging technologies 1
- Geunho Cho, Fabrizio Lombardi:
A novel and improved design of a ternary CNTFET-based cell. 131-136 - Arne Heittmann, Tobias G. Noll:
Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits. 137-142 - Yi Zhou, Chao Zhang, Guangyu Sun, Kun Wang, Yu Zhang:
Asymmetric-access aware optimization for STT-RAM caches with process variations. 143-148
VLSI design 1
- Yoshiro Riho, Kazuo Nakazato:
A new extension method of retention time for memory cell on dynamic random access memory. 149-154 - Abdulkadir Akin, Ipek Baz, Baris Atakan, Irem Boybat
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware. 155-160 - Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
A source-synchronous Htree-based network-on-chip. 161-166 - Uwe Deidersen, Dominik Auras, Gerd Ascheid:
A parallel VLSI architecture for Markov chain Monte Carlo based MIMO detection. 167-172
CAD 2
- Lingyi Liu, Shobha Vasudevan:
Scaling RTL property checking using feasible path analysisand decomposition. 173-178 - Levent Aksoy
SIREN: a depth-first search algorithm for the filter design optimization problem. 179-184 - Chen-Hsuan Lin, Lingyi Liu, Shobha Vasudevan:
Generating concise assertions with complete coverage. 185-190 - Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. 191-196
GLSVLSI keynote
- Christian Piguet:
Electronics for a greener planet. 197-202
Clock trees
- Jin-Tai Yan, Zhi-Wei Chen:
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. 203-208 - Can Sitik, Baris Taskin:
Multi-corner multi-voltage domain clock mesh design. 209-214
Test 2
- Shuai Wang, Guangshan Duan, Chuanlei Zheng, Tao Jin:
Combating NBTI-induced aging in data caches. 215-220 - Simone Corbetta, William Fornaciari
Performance/reliability trade-off in superscalar processors for aggressive NBTI restoration of functional units. 221-226
Reconfigurable designs
- Sandeep Miryala, Andrea Calimera
Delay model for reconfigurable logic gates based on graphene PN-junctions. 227-232 - Qin Wang, Arne Heittmann, Tobias G. Noll:
Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays. 233-238 - Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
DRMA: dynamically reconfigurable MPSoC architecture. 239-244 - Miguel Morales-Sandoval
A compact FPGA-based montgomery multiplier over prime fields. 245-250
VLSI specialized units
- Evangelos Vassalos, Dimitris Bakalis
On the design of modulo 2n-1 cubing units. 251-256 - Aristides Efthymiou
An error tolerant CAM with nand match-line organization. 257-262 - Kiamal Z. Pekmestzi, Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis:
Efficient modulo 2n+1 multiplication for the idea block cipher. 263-268 - Neela Gopi, Jeffrey Draper:
An asymmetric adaptive-precision energy-efficient 3DIC multiplier. 269-274
CAD for 3D
- Caleb Serafy, Bing Shi, Ankur Srivastava
Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs. 275-280 - Bing Shi, Ankur Srivastava
Thermal stress aware 3D-IC statistical static timing analysis. 281-286 - Suhas M. Satheesh, Emre Salman:
Effect of TSV fabrication technology on power distribution in 3D ICs. 287-292
Design and modeling
- Yirong Zhao, Jiayin Li, Kartik Mohanram:
Multi-port FinFET SRAM design. 293-298 - Mohammad Yousef Zarei, Reza Asadpour, Siamak Mohammadi
Modeling symmetrical independent gate FinFET using predictive technology model. 299-304 - Amin Farshidi, Logan M. Rakai, Laleh Behjat
A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications. 305-310
Poster session 1
- Po-Han Huang, Huang-Lun Lin, Hsien-Ching Hsieh, Chi-Hung Lin, Shui-An Wen, Yi-Fa Sun:
Low power 3-D stacking multimedia platform with reconfigurable memory architecture. 311-312 - Nikola Katic, Mahdad Hosseini Kamal, Mustafa Kilic, Alexandre Schmid
High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]. 313-314 - Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake:
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. 315-316 - Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle:
An evaluation of an AES implementation protected against EM analysis. 317-318 - Eyal-Itzhak Nave, Ran Ginosar:
PBD: packet buffer DVFs. 319-320 - Aroua Briki, Cyrille Chavet, Philippe Coussy:
A memory mapping approach for network and controller optimization in parallel interleaver architectures. 321-322 - Tsun-Ming Tseng
Post-route refinement for high-frequency PCBs considering meander segment alleviation. 323-324 - Nan Li, Elena Dubrova:
On-chip area-efficient binary sequence storage. 325-326 - Hailang Wang, Emre Salman:
Power gating topologies in TSV based 3D integrated circuits. 327-328 - Amr Elshennawy, Craig M. Marianno, Sunil P. Khatri:
Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector. 329-330
Poster session 2
- Mahmoud Elbayoumi, Michael S. Hsiao, Mustafa Y. ElNainay
Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract. 331-332 - Azam Seyedi, Gulay Yalcin, Osman S. Unsal
Circuit design of a novel adaptable and reliable L1 data cache. 333-334 - Vinod Pangracious
Physical design exploration of 3D tree-based FPGA architecture. 335-336 - Bing Shi, Caleb Serafy, Ankur Srivastava
Co-optimization of TSV assignment and micro-channel placement for 3D-ICs. 337-338 - Yao Wang, Sorin Dan Cotofana
Lifetime reliability assessment with aging information from low-level sensors. 339-340 - Christos Kyrkou
A hardware-efficient architecture for embedded real-time cascaded support vector machines classification. 341-342 - Yazhuo Dong, Wu Zhan, Xiqing Ye:
Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources. 343-344 - Meeta Srivastav, Yongbo Zuo, Xu Guo, Leyla Nazhandali, Patrick Schaumont
Study of ASIC technology impact factors on performance evaluation of SHA-3 candidates. 345-346 - Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained replacement using spare cells for design changes. 347-348 - Ying Teng, Baris Taskin:
Rotary traveling wave oscillator frequency division at nanoscale technologies. 349-350 - Arighna Deb, Debesh K. Das, Hafizur Rahaman
Reversible synthesis of symmetric boolean functions based on unate decomposition. 351-352
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