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Mengjie Mao
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2020 – today
- 2021
- [j6]Xiaoxiao Liu
, Mengjie Mao
Exploring Applications of STT-RAM in GPU Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 238-249 (2021)
2010 – 2019
- 2019
- [j5]Bing Li
Thread Batching for High-performance Energy-efficient GPU Memory Design. ACM J. Emerg. Technol. Comput. Syst. 15(4): 39:1-39:21 (2019) - [i1]Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai Helen Li:
Thread Batching for High-performance Energy-efficient GPU Memory Design. CoRR abs/1906.05922 (2019) - 2018
- [j4]Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge:
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1985-1998 (2018) - 2017
- [j3]Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. IEEE Trans. Computers 66(9): 1478-1490 (2017) - [j2]Xiuyuan Bi
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1807-1820 (2017) - 2016
- [j1]Xiaoxiao Liu
Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 617-628 (2016) - [c21]Mengjie Mao, Wujie Wen, Xiaoxiao Liu
TEMP: thread batch enabled memory partitioning for GPU. DAC 2016: 65:1-65:6 - [c20]Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen:
Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache. DATE 2016: 762-767 - [c19]Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge:
A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations. DATE 2016: 1285-1290 - [c18]Sicheng Li, Xiaoxiao Liu
Heterogeneous systems with reconfigurable neuromorphic computing accelerators. ISCAS 2016: 125-128 - 2015
- [c17]Xiaoxiao Liu
An efficient STT-RAM-based register file in GPU architectures. ASP-DAC 2015: 490-495 - [c16]Xiaoxiao Liu
RENO: a high-efficient reconfigurable neuromorphic computing accelerator design. DAC 2015: 66:1-66:6 - [c15]Mengjie Mao, Jingtong Hu
VWS: a versatile warp scheduler for exploring diverse cache localities of GPGPU applications. DAC 2015: 83:1-83:6 - [c14]Hai Li
The applications of memristor devices in next-generation cortical processor designs. ISCAS 2015: 17-20 - 2014
- [c13]Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones
Prefetching techniques for STT-RAM based last-level cache in CMP systems. ASP-DAC 2014: 67-72 - [c12]Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen:
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. DAC 2014: 35:1-35:6 - [c11]Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. DAC 2014: 196:1-196:6 - [c10]Xiaoxiao Liu
A heterogeneous computing system with memristor-based neuromorphic accelerators. HPEC 2014: 1-6 - [c9]Hai Li
Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). ISIC 2014: 124-127 - [c8]Hai Li
Emerging memristor technology enabled next generation cortical processor. SoCC 2014: 377-382 - 2013
- [c7]Mengjie Mao, Hai (Helen) Li
Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. ACM Great Lakes Symposium on VLSI 2013: 55-60 - [c6]Wujie Wen, Mengjie Mao, Xiaochun Zhu, Seung-Hyuk Kang, Danghui Wang, Yiran Chen:
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors. ICCAD 2013: 1-8 - [c5]Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li
Unleashing the potential of MLC STT-RAM caches. ICCAD 2013: 429-436 - 2012
- [c4]Mengjie Mao, Hong An, Tao Sun, Qi Li, Bobin Deng, Xuechao Wei, Junrui Zhou:
Distributed Control Independence for Composable Multi-processors. ACIS-ICIS 2012: 124-129 - [c3]Bobin Deng, Hong An, Qi Li, Gongming Li, Mengjie Mao:
Value Predicted LogSPoTM: Improve the Parallesim of Thread Level System by Using a Value Predictor. ACIS-ICIS 2012: 130-135 - [c2]Mengjie Mao, Hong An, Bobin Deng, Tao Sun, Xuechao Wei, Wei Zhou, Wenting Han:
Distributed replay protocol for distributed uniprocessors. ICS 2012: 3-14 - 2010
- [c1]Tao Sun, Hong An, Yongqing Ren, Mengjie Mao, Yang Liu, Mu Xu, Qi Li:
FACRA: Flexible-Core Architecture Chip Resource Abstractor. PDCAT 2010: 440-447
Coauthor Index
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