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"Efficient transistor-level design of CMOS gates."

Vinicius N. Possani et al. (2013)

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DOI: 10.1145/2483028.2483089

access: closed

type: Conference or Workshop Paper

metadata version: 2020-07-10

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  - conf/glvlsi/PossaniCRRMJ13
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  - https://dblp.org/rec/conf/glvlsi/PossaniCRRMJ13
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI 2013: 191-196

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