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Aristides Efthymiou
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2020 – today
- 2024
- [c18]Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas:
Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. ICAIIC 2024: 401-406 - [c17]Ioannis Rizos, Georgios Papatheodorou, Aristides Efthymiou:
Exploring the Design Space of 32x32 Approximate Reduced Complexity Wallace Multipliers. MOCAST 2024: 1-4 - 2022
- [c16]Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas:
Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. BlackSeaCom 2022: 303-309 - 2021
- [c15]Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas:
An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. MeditCom 2021: 378-382
2010 – 2019
- 2013
- [c14]Aristides Efthymiou:
An error tolerant CAM with nand match-line organization. ACM Great Lakes Symposium on VLSI 2013: 257-262 - 2010
- [j4]Aristides Efthymiou:
Initialization-Based Test Pattern Generation for Asynchronous Circuits. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 591-601 (2010) - [c13]Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume:
Optimising Self-Timed FPGA Circuits. DSD 2010: 563-570
2000 – 2009
- 2008
- [c12]Dilip P. Vasudevan, Aristides Efthymiou:
A Partial Scan Based Test Generation for Asynchronous Circuits. DDECS 2008: 186-189 - 2007
- [c11]Rahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou:
Synthetic Trace-Driven Simulation of Cache Memory. AINA Workshops (1) 2007: 764-771 - [c10]Aristides Efthymiou:
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits. DDECS 2007: 377-382 - 2005
- [j3]Aristides Efthymiou, John Bainbridge, Douglas A. Edwards:
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1384-1393 (2005) - [c9]Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou:
A Low-Power Processor Architecture Optimized forWireless Devices. ASAP 2005: 185-190 - [c8]Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou:
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156 - 2004
- [j2]Aristides Efthymiou, Jim D. Garside:
A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 325-329 (2004) - [c7]Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury:
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215 - [c6]Aristides Efthymiou, John Bainbridge, Douglas A. Edwards:
Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23 - [c5]Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards:
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. DATE 2004: 672-673 - 2003
- [c4]Aristides Efthymiou, Jim D. Garside:
Adaptive Pipeline Structures fo Speculation Control. ASYNC 2003: 46-55 - 2002
- [c3]Aristides Efthymiou, Jim D. Garside:
Adaptive Pipeline Depth Control for Processor Power-Management. ICCD 2002: 454-457 - [c2]Aristides Efthymiou, Jim D. Garside:
An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED 2002: 136-141 - 2001
- [j1]Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple:
Power Management in the Amulet Microprocessors. IEEE Des. Test Comput. 18(2): 42-52 (2001)
1990 – 1999
- 1995
- [c1]Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou:
Pipelined Memory Shared Buffer for VLSI Switches. SIGCOMM 1995: 39-48
Coauthor Index
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