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Shobha Vasudevan
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2020 – today
- 2024
- [j16]Debjit Pal
, Shobha Vasudevan
ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2810-2824 (2024) - 2021
- [c44]Shobha Vasudevan, Wenjie Jiang, David Bieber, Rishabh Singh, Hamid Shojaei, Richard Ho, Charles Sutton:
Learning Semantic Representations to Verify Hardware Designs. NeurIPS 2021: 23491-23504 - [i1]Debjit Pal, Shobha Vasudevan:
Feature Engineering for Scalable Application-Level Post-Silicon Debugging. CoRR abs/2102.04554 (2021) - 2020
- [j15]Debjit Pal
Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 533-546 (2020) - [j14]Debjit Pal
Assertion Ranking Using RTL Source Code Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1711-1724 (2020)
2010 – 2019
- 2019
- [c43]Samuel Hertz, Debjit Pal
A figure of merit for assertions in verification. ASP-DAC 2019: 675-680 - [c42]Keven Feng, Sandeep Vora, Rui Jiang, Elyse Rosenbaum, Shobha Vasudevan:
Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors. DATE 2019: 156-161 - 2018
- [c41]Jiayi Duan, Ziheng Zeng, Alina Oprea, Shobha Vasudevan:
Automated Generation and Selection of Interpretable Features for Enterprise Security. IEEE BigData 2018: 1258-1265 - [c40]Debjit Pal
Application level hardware tracing for scaling post-silicon debug. DAC 2018: 92:1-92:6 - 2017
- [j13]Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
A novel test compression algorithm for analog circuits to decrease production costs. Integr. 58: 538-548 (2017) - [c39]Shobha Vasudevan:
Still a Fight to Get It Right: Verification in the Era of Machine Learning. ICRC 2017: 1-8 - 2016
- [j12]Seyed Nematollah Adel Ahmadyan
Automated Transient Input Stimuli Generation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 858-871 (2016) - [c38]Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
Every test makes a difference: Compressing analog tests to decrease production costs. ASP-DAC 2016: 539-544 - [c37]Seyed Nematollah Ahmadyan, Shobha Vasudevan:
Duplex: simultaneous parameter-performance exploration for optimizing analog circuits. ICCAD 2016: 19 - [c36]Debjit Pal
Symptomatic Bug Localization for Functional Debug of Hardware Designs. VLSID 2016: 517-522 - 2015
- [c35]Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan:
Fast eye diagram analysis for high-speed CMOS circuits. DATE 2015: 1377-1382 - [c34]Qiao Jin, Jiayi Duan, Shobha Vasudevan, Michael D. Bailey:
Packer classifier based on PE header information. HotSoS 2015: 19:1-19:2 - [c33]Sai Ma, Debjit Pal
Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. ICCAD 2015: 1-8 - 2014
- [j11]Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan:
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 945-958 (2014) - [j10]Lingyi Liu, Shobha Vasudevan:
Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL. ACM Trans. Design Autom. Electr. Syst. 20(1): 4:1-4:33 (2014) - [c32]Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan:
Code Coverage of Assertions Using RTL Source Code Analysis. DAC 2014: 61:1-61:6 - [c31]David Sheridan, Lingyi Liu, Hyungsul Kim, Shobha Vasudevan:
A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. VLSID 2014: 68-73 - 2013
- [j9]Lingyi Liu, Shobha Vasudevan:
Automatic Generation of System Level Assertions from Transaction Level Models. J. Electron. Test. 29(5): 669-684 (2013) - [j8]Jayanand Asok Kumar, Shobha Vasudevan:
Formal Probabilistic Timing Verification in RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 788-801 (2013) - [j7]Samuel Hertz, David Sheridan, Shobha Vasudevan:
Mining Hardware Assertions With Guidance From Static Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 952-965 (2013) - [c30]Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. DATE 2013: 21-26 - [c29]Seyed Nematollah Ahmadyan, Shobha Vasudevan:
Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. DATE 2013: 1436-1441 - [c28]Lingyi Liu, Shobha Vasudevan:
Scaling RTL property checking using feasible path analysisand decomposition. ACM Great Lakes Symposium on VLSI 2013: 173-178 - [c27]Chen-Hsuan Lin, Lingyi Liu, Shobha Vasudevan:
Generating concise assertions with complete coverage. ACM Great Lakes Symposium on VLSI 2013: 185-190 - [c26]Lingyi Liu, Xuanyu Zhong, Xiaotao Chen, Shobha Vasudevan:
Diagnosing root causes of system level performance violations. ICCAD 2013: 295-302 - [c25]Parth Sagdeo, Nicholas Ewalt, Debjit Pal
Using automatically generated invariants for regression testing and bug localization. ASE 2013: 634-639 - 2012
- [j6]Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan:
A Technique for Test Coverage Closure Using GoldMine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 790-803 (2012) - [j5]Jayanand Asok Kumar, Shobha Vasudevan:
Formal Performance Analysis for Faulty MIMO Hardware. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1914-1918 (2012) - [c24]Jayanand Asok Kumar, Shobha Vasudevan:
Verifying dynamic power management schemes using statistical model checking. ASP-DAC 2012: 579-584 - [c23]Viraj Athavale, Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl, Shobha Vasudevan:
Using static analysis for coverage extraction fromemulation/prototyping platforms. CODES+ISSS 2012: 207-214 - [c22]Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan:
Early prediction of NBTI effects using RTL source code analysis. DAC 2012: 808-813 - [c21]Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan:
Goal-oriented stimulus generation for analog circuits. DAC 2012: 1018-1023 - [c20]Lingyi Liu, Chen-Hsuan Lin, Shobha Vasudevan:
Word level feature discovery to enhance quality of assertion mining. ICCAD 2012: 210-217 - 2011
- [c19]Lingyi Liu, David Sheridan, William Tuohy, Shobha Vasudevan:
Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. DATE 2011: 173-178 - [c18]Lingyi Liu, Shobha Vasudevan:
Efficient validation input generation in RTL by hybridized source code analysis. DATE 2011: 1596-1601 - [c17]Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan:
Scaling probabilistic timing verification of hardware using abstractions in design source code. FMCAD 2011: 196-205 - [c16]Hyungsul Kim, Sungjin Im, Tarek F. Abdelzaher, Jiawei Han, David Sheridan, Shobha Vasudevan:
Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink. ICDM 2011: 330-339 - [c15]Parth Sagdeo, Viraj Athavale, Sumant Kowshik, Shobha Vasudevan:
PRECIS: Inferring invariants using program path guided clustering. ASE 2011: 532-535 - [c14]Lingyi Liu, David Sheridan, Viraj Athavale, Shobha Vasudevan:
Automatic generation of assertions from system level design using data mining. MEMOCODE 2011: 191-200 - [c13]Jayanand Asok Kumar, Shobha Vasudevan:
Variation-Conscious Formal Timing Verification in RTL. VLSI Design 2011: 58-63 - [c12]Shobha Vasudevan:
Coverage closure in SoC verification: Are we chasing a mirage? VTS 2011: 211 - 2010
- [c11]Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson:
GoldMine: Automatic assertion generation using data mining and static analysis. DATE 2010: 626-629 - [c10]Jayanand Asok Kumar, Shobha Vasudevan:
Statistical guarantees of performance for MIMO designs. DSN 2010: 467-476 - [c9]Jayanand Asok Kumar, Shobha Vasudevan:
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. QEST 2010: 143-152
2000 – 2009
- 2009
- [j4]Vinod Viswanath
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. J. Low Power Electron. 5(3): 339-353 (2009) - [c8]Lingyi Liu, Shobha Vasudevan:
STAR: Generating input vectors for design validation by static analysis of RTL. HLDVT 2009: 32-37 - [c7]Vinod Viswanath
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. VLSI Design 2009: 77-82 - 2008
- [j3]Shobha Vasudevan, Vinod Viswanath
Sequential equivalence checking between system level and RTL descriptions. Des. Autom. Embed. Syst. 12(4): 377-396 (2008) - 2007
- [j2]Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham:
Improved verification of hardware designs through antecedent conditioned slicing. Int. J. Softw. Tools Technol. Transf. 9(1): 89-101 (2007) - [j1]Shobha Vasudevan, Vinod Viswanath
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers 56(10): 1401-1414 (2007) - [c6]Shobha Vasudevan, Vinod Viswanath
Efficient Microprocessor Verification using Antecedent Conditioned Slicing. VLSI Design 2007: 43-49 - 2006
- [c5]Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham:
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. ITC 2006: 1-9 - [c4]Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu:
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. MEMOCODE 2006: 71-80 - 2005
- [c3]S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham:
Automated mapping of pre-computed module-level test sequences to processor instructions. ITC 2005: 10 - 2004
- [c2]Shobha Vasudevan, Jacob A. Abraham:
Static program transformations for efficient software model checking. IFIP Congress Topical Sessions 2004: 257-281 - [c1]Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham:
Efficient Model Checking of Hardware Using Conditioned Slicing. AVoCS 2004: 279-294
Coauthor Index
aka: Seyed Nematollah Adel Ahmadyan
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