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"Delay model for reconfigurable logic gates based on graphene PN-junctions."

Sandeep Miryala et al. (2013)

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DOI: 10.1145/2483028.2483099

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/glvlsi/MiryalaCMP13
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  - https://dblp.org/rec/conf/glvlsi/MiryalaCMP13
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI 2013: 227-232

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