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22nd Asian Test Symposium 2013: Yilan County, Taiwan
- 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013. IEEE Computer Society 2013, ISBN 978-0-7695-5080-0
Session 4A: 3D-IC Design-for-Test
- Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
:
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. 1-6 - Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li:
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs. 7-12 - Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. 13-18
Session 4B: Power/Thermal Aware Testing I
- Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. 19-24 - Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay:
Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during Testing. 25-30 - Stephan Eggersglüß:
Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill. 31-36
Session 5A: At-Speed Testing
- Fang Bao, Mohammad Tehranipoor, Harry H. Chen:
Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise. 37-42 - Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu
Test Generation of Path Delay Faults Induced by Defects in Power TSV. 43-48 - Kun-Han Tsai, Xijiang Lin:
Multicycle-aware At-speed Test Methodology. 49
Session 5B: Analog/Mixed-Signal Test
- Sen-Wen Hsiao, Xian Wang, Abhijit Chatterjee:
Analog Sensor Based Testing of Phase-Locked Loop Dynamic Performance Parameters. 50-55 - Xian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee:
Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe Measurements. 56-61 - Long-Yi Lin, Hao-Chiao Hong
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model. 62-66
Session 6A: Diagnosis and Debugging
- Masafumi Nikaido, Yukihisa Funatsu, Tetsuya Seiyama, Junpei Nonaka, Kazuki Shigeta:
Failure Localization of Logic Circuits Using Voltage Contrast Considering State of Transistors. 67-72 - Fangming Ye, Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty
Handling Missing Syndromes in Board-Level Functional-Fault Diagnosis. 73-78 - Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja:
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. 79-84
Session 6B: Design-for-Test I
- Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue:
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. 85-90 - Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator. 91-96 - Wei-Cheng Lien
A New LFSR Reseeding Scheme via Internal Response Feedback. 97-102
Session 6C: Industry Session I
- Guoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang:
Scan Test Data Volume Reduction for SoC Designs in EDT Environment. 103-104 - Peter Sarson, Gregor Schatzberger, Robert Seitz:
Automotive EEPROM Qualification and Cost Optimization. 105-106 - Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. 107-108
Session 7A: Memory Defects
- Elena I. Vatajelu
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. 109-114 - Da Cheng, Hsunwei Hsiung, Bin Liu, Jianing Chen, Jia Zeng, Ramesh Govindan, Sandeep K. Gupta:
A New March Test for Process-Variation Induced Delay Faults in SRAMs. 115-122 - Bing-Chuan Bai
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. 123-127
Session 7B: Converter Testing
- Hsun-Cheng Lee, Jacob A. Abraham:
Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction. 128-133 - Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh:
Digital Compensation for Timing Mismatches in Interleaved ADCs. 134-139 - Kentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai:
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators. 140-146
Session 8A: 3D-IC Interposer Test
- Ran Wang, Krishnendu Chakrabarty
Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs. 147-152 - Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
Mid-bond Interposer Wire Test. 153-158 - Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package. 159-164
Session 8B: Power/Thermal Aware Testing II
- Spencer K. Millican, Kewal K. Saluja:
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling. 165-170 - Kohei Miyase, Matthias Sauer, Bernd Becker
Search Space Reduction for Low-Power Test Generation. 171-176 - Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian:
MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. 177-182
Session 9A: Defect-Based Test
- Yasuo Sato, Seiji Kajihara:
A Stochastic Model for NBTI-Induced LSI Degradation in Field. 183-188 - Chao Han, Adit D. Singh:
Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects. 189-194
Session 9B: Design-for-Test II
- Chin Hai Ang:
Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG Testing. 195-200 - Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht:
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. 201-206 - Dong Xiang:
A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing. 207-212
Session 9C: Industry Session II
- Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong:
Multi-histogram ADC BIST System for ADC Linearity Testing. 213-214
Session 10A: Memory Testing
- Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning:
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. 215-220 - Chih-Sheng Hou, Jin-Fu Li:
Testing Disturbance Faults in Various NAND Flash Memories. 221-226 - Paolo Bernardi
An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase. 227-232
Session 10B: Automatic Test Pattern Generation
- Kelson Gent, Michael S. Hsiao:
Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking. 233-238 - Yanhong Zhou, Tiancheng Wang, Tao Lv, Huawei Li, Xiaowei Li:
Path Constraint Solving Based Test Generation for Hard-to-Reach States. 239-244 - Dominik Erb, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
Accurate Multi-cycle ATPG in Presence of X-Values. 245-250
Session 11A: Process Variations
- Hsunwei Hsiung, Da Cheng, Bin Liu, Ramesh Govindan, Sandeep K. Gupta:
Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations. 251-258 - Jifeng Chen, Mohammad Tehranipoor:
Critical Paths Selection and Test Cost Reduction Considering Process Variations. 259-264 - Shuo-You Hsu, Chih-Hsiang Hsu, Ting-Shuo Hsu, Jing-Jia Liou:
A Region-Based Framework for Design Feature Identification of Systematic Process Variations. 265-270
Session 11B: High-Speed I/O Testing
- Jose Moreira, Bernhard Roth, Hubert Werkmann, Lars Klapproth, Michael Howieson, Mark Broman, Wend Ouedraogo, Mitchell Lin:
An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System. 271-276 - Suvadeep Banerjee
Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus. 277-282 - Debesh Bhatta, Nicholas Tzou, Sen-Wen Hsiao, Abhijit Chatterjee:
Time Domain Reconstruction of Incoherently Undersampled Periodic Waveforms Using Bandwidth Interleaving. 283-288
Session 11C: Yield Enhancement and Security
- Tong-Yu Hsieh, Yi-Han Peng, Chia-Chi Ku:
An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance. 289-294 - Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Securing Access to Reconfigurable Scan Networks. 295-300 - Wooheon Kang, Changwook Lee, Keewon Cho, Sungho Kang:
A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories. 301-306
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