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Chien-Mo James Li
James Chien-Mo Li – J. C.-M. Li
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- affiliation: National Taiwan University, Taipei, Taiwan
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2020 – today
- 2024
- [j35]Cheng-Yun Hsieh
, Hsin-Ying Tsai, Yuan-Hsiang Lu, James Chien-Mo Li
Small Sampling Overhead Error Mitigation for Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 826-839 (2024) - [c67]Hsu-Yu Huang, Chu-Yun Hsiao, Tsung-Te Liu, James Chien-Mo Li:
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips. DAC 2024: 82:1-82:6 - [c66]Xin-Ping Chen, Hsu-Yu Huang, Chu-Yun Hsiao, Jennifer Shueh-Inn Hu, James Chien-Mo Li:
Test Compression for Neuromorphic Chips. ETS 2024: 1-6 - [c65]Wei-Shen Wang, Zhe-Jia Liang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li:
Thermal-Aware Test Frequency Optimization. ITC-Asia 2024: 1-5 - 2023
- [c64]Zhe-Jia Liang, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li:
High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns. ITC 2023: 206-215 - [c63]Bing-Han Hsieh, Yun-Sheng Liu, James Chien-Mo Li, Chris Nigh, Mason Chern, Gaurav Bhargava:
Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. ITC 2023: 293-302 - [c62]Chun Chen, Jeng-Yu Liao, James Chien-Mo Li, Harry H. Chen, Eric Jia-Wei Fang:
Vmin Prediction Using Nondestructive Stress Test. VTS 2023: 1-7 - [c61]Yu-Min Li, Cheng-Yun Hsieh
Diagnosis of Quantum Circuits in the NISQ Era. VTS 2023: 1-7 - 2022
- [c60]Jia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chien-Mo James Li, Norman Chang, Ying-Shiun Li, Wentze Chuang:
Vector-based Dynamic IR-drop Prediction Using Machine Learning. ASP-DAC 2022: 202-207 - [c59]I-Wei Chiu
Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips. ICCAD 2022: 30:1-30:7 - [c58]Shi-Tang Liu, Jia-Xian Chen, Yu-Tsung Wu, Chao-Ho Hsieh, Chien-Mo James Li, Norman Chang, Ying-Shiun Li, Wentze Chuang:
Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor. ISQED 2022: 27-32 - [c57]Cheng-Sian Kuo, Bing-Han Hsieh, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava, Mason Chern:
Diagnosing Double Faulty Chains through Failing Bit Separation. ITC 2022: 175-184 - [c56]Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. ITC 2022: 213-218 - 2021
- [j34]Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. J. Electron. Test. 37(4): 453-471 (2021) - [c55]Hsiao-Yin Tseng, I-Wei Chiu
Machine Learning-Based Test Pattern Generation for Neuromorphic Chips. ICCAD 2021: 1-7 - [c54]Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. ITC 2021: 47-52 - [c53]Mu-Ting Wu, Cheng-Sian Kuo, James Chien-Mo Li, Chris Nigh
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization. ITC 2021: 251-259 - [c52]Yi-Zhan Hsieh, Hsiao-Yin Tseng, I-Wei Chiu
Fault Modeling and Testing of Spiking Neural Network Chips. ITC-Asia 2021: 1-6 - [c51]Min-Yan Su, Wei-Chen Lin, Yen-Ting Kuo, Chien-Mo James Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
Chip Performance Prediction Using Machine Learning Techniques. VLSI-DAT 2021: 1-4 - 2020
- [c50]Chih-Yan Liu, Mu-Ting Wu, James Chien-Mo Li, Gaurav Bhargava, Chris Nigh
Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips. ATS 2020: 1-7 - [c49]Cheng-Yun Hsieh
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits. DAC 2020: 1-6 - [c48]Chen-Hung Wu, Cheng-Yun Hsieh
qATG: Automatic Test Generation for Quantum Circuits. ITC 2020: 1-10 - [c47]Heng-Yi Lin, Yen-Chun Fang, Shi-Tang Liu, Jia-Xian Chen, Chien-Mo James Li, Eric Jia-Wei Fang:
Automatic IR-Drop ECO Using Machine Learning. ITC-Asia 2020: 7-12 - [c46]Yan-Shen You, Chih-Yan Liu, Mu-Ting Wu, Po-Wei Chen, James Chien-Mo Li:
Diagnosis technique for Clustered Multiple Transition Delay Faults. ITC-Asia 2020: 53-58 - [c45]Ming-Ting Lee, Chen-Hung Wu, Shi-Tang Liu, Cheng-Yun Hsieh, James Chien-Mo Li:
High Efficiency and Low Overkill Testing for Probabilistic Circuits. ITC-Asia 2020: 83-87
2010 – 2019
- 2019
- [j33]Shih-An Hsieh, Ying-Hsu Wang, Ting-Yu Shen, Kuan-Yen Huang, Chia-Cheng Pai, Tsai-Chieh Chen
DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 136-148 (2019) - [c44]Kai-Chieh Yang, Ming-Ting Lee, Chen-Hung Wu, James Chien-Mo Li:
ATPG and Test Compression for Probabilistic Circuits. VLSI-DAT 2019: 1-4 - 2018
- [j32]Runqing Cao, James Chien-Mo Li, Lei Zuo, Zeyu Wang, Yunlong Lu:
A new method for parameter estimation of high-order polynomial-phase signals. Signal Process. 142: 212-222 (2018) - [c43]Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang:
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC 2018: 45:1-45:6 - [c42]Yen-Chun Fang, Heng-Yi Lin, Min-Yan Su, Chien-Mo James Li, Eric Jia-Wei Fang:
Machine-learning-based dynamic IR drop prediction for ECO. ICCAD 2018: 17 - [c41]Ting-Yu Shen, Chia-Cheng Pai, Tsai-Chieh Chen, James Chien-Mo Li, Samuel Pan:
Test methodology for PCHB/PCFB Asynchronous Circuits. ITC 2018: 1-8 - [c40]Yu-Wei Chen, Yu-Hao Ho, Chih-Ming Chang, Kai-Chieh Yang, Ming-Ting Li, James Chien-Mo Li:
Parallel order ATPG for test compaction. VLSI-DAT 2018: 1-4 - [c39]Yu-Ching Li, Shih-Yao Lin, Heng-Yi Lin, James Chien-Mo Li:
Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations. VLSI-DAT 2018: 1-4 - [c38]Shih-Yao Lin, Yen-Chun Fang, Yu-Ching Li, Yu-Cheng Liu, Tsung-Shan Yang, Shang-Chien Lin, Chien-Mo James Li, Eric Jia-Wei Fang:
IR drop prediction of ECO-revised circuits using machine learning. VTS 2018: 1-6 - 2017
- [j31]Yu-Cheng Liu, Cheng-Yu Han, Shih-Ya Lin, James Chien-Mo Li:
PSN-aware circuit test timing prediction using machine learning. IET Comput. Digit. Tech. 11(2): 60-67 (2017) - [c37]Chih-Ming Chang, Kai-Jie Yang, James Chien-Mo Li, Hung Chen:
Test Pattern Compression for Probabilistic Circuits. ATS 2017: 23-27 - [c36]Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo James Li:
Test Methodology for Dual-rail Asynchronous Circuits. DAC 2017: 37:1-37:6 - [c35]Po-Hao Chen, Chi-Lin Lee, Jing-Yu Chen, Po-Wei Chen, James Chien-Mo Li:
Physical-aware diagnosis of multiple interconnect defects. ITC-Asia 2017: 40-45 - [c34]Yu-Hao Ho, Yo-Wei Chen, Chih-Ming Chang, Kai-Chieh Yang, James Chien-Mo Li:
Robust test pattern generation for hold-time faults in nanometer technologies. VLSI-DAT 2017: 1-4 - 2016
- [j30]Cheng-Yu Han, Yu-Ching Li, Hao-Tien Kan, James Chien-Mo Li:
Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2320-2327 (2016) - [j29]Hung-I Lee, Chen-Yo Han, James Chien-Mo Li:
A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1130-1137 (2016) - [j28]Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen:
Test Pattern Modification for Average IR-Drop Reduction. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 38-49 (2016) - 2015
- [c33]Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li:
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. ATS 2015: 181-186 - [c32]Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, James Chien-Mo Li:
TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects. VLSI-DAT 2015: 1-4 - 2014
- [j27]Po-Juei Chen, Chieh-Chih Che, J. C.-M. Li, Shuo-Fen Kuo, Pei-Ying Hsueh, Chun-Yi Kuo, Jih-Nung Lee:
Physical-aware systematic multiple defect diagnosis. IET Comput. Digit. Tech. 8(5): 199-209 (2014) - [j26]Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li:
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 24-35 (2014) - [j25]Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 667-674 (2014) - [j24]Ming-Hong Tsai, Wei-Sheng Ding, Hung-Yi Hsieh, James Chien-Mo Li:
Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1980-1989 (2014) - [c31]Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang:
GPU-based timing-aware test generation for small delay defects. ETS 2014: 1-2 - [c30]Shih-Min Chao, Po-Juei Chen, Jing-Yu Chen, Po-Hao Chen, Ang-Feng Lin, James Chien-Mo Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li:
Divide and conquer diagnosis for multiple defects. ITC 2014: 1-8 - 2013
- [j23]Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau:
Compact Test Pattern Selection for Small Delay Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 971-975 (2013) - [c29]Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu
Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium 2013: 43-48 - [c28]Bing-Chuan Bai
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium 2013: 123-127 - [c27]Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li:
GPU-based n-detect transition fault ATPG. DAC 2013: 28:1-28:8 - [c26]Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li:
Automatic test pattern generation for delay defects using timed characteristic functions. ICCAD 2013: 91-98 - 2012
- [j22]Wei-Lin Tsai, Wei-Chih Liu, James Chien-Mo Li:
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis. IEEE Trans. Computers 61(7): 928-938 (2012) - [j21]Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen:
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1644-1655 (2012) - [j20]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang:
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. ACM Trans. Design Autom. Electr. Syst. 17(4): 48:1-48:16 (2012) - [j19]Geng-Ming Chiu, James Chien-Mo Li:
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 126-134 (2012) - [c25]Chih-Yao Hsu, Chun-Yi Kuo, James Chien-Mo Li, Krishnendu Chakrabarty
3D IC test scheduling using simulated annealing. VLSI-DAT 2012: 1-4 - 2011
- [j18]Chester Liu, En-Hua Ma, Wen-En Wei, Chien-Mo James Li, I-Chun Cheng
Placement Optimization of Flexible TFT Digital Circuits. IEEE Des. Test Comput. 28(6): 24-31 (2011) - [j17]Chi-Hsuan Cheng, James Chien-Mo Li:
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology. J. Electron. Test. 27(2): 193-201 (2011) - [j16]W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang:
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. IET Comput. Digit. Tech. 5(4): 238-246 (2011) - [j15]Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu:
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 455-463 (2011) - [j14]Kuan-Yu Liao, Chia-Yuan Chang, James Chien-Mo Li:
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1767-1772 (2011) - [c24]Po-Juei Chen, Wei-Li Hsu
An Accurate Timing-Aware Diagnosis Algorithm for Multiple Small Delay Defects. Asian Test Symposium 2011: 291-296 - [c23]Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen:
An at-speed self-testable technique for the high speed domino adder. CICC 2011: 1-4 - [c22]Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
Test clock domain optimization for peak power supply noise reduction during scan. ITC 2011: 1-8 - 2010
- [j13]Wei-Chung Kao, Wei-Shun Chuang, Shiu-Ting Lin, Chien-Mo James Li, Vasco Manquinho
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 392-400 (2010) - [c21]Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li:
Static timing analysis for flexible TFT circuits. DAC 2010: 799-802 - [c20]Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li:
CSER: BISER-based concurrent soft-error resilience. VTS 2010: 153-158
2000 – 2009
- 2009
- [j12]F.-M. Wang, W.-C. Wang, James Chien-Mo Li:
Time-space test response compaction and diagnosis based on BCH codes. IET Comput. Digit. Tech. 3(3): 304-313 (2009) - [c19]Bing-Chuan Bai
Fault modeling and testing of retention flip-flops in low power designs. ASP-DAC 2009: 684-689 - [c18]Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, James Chien-Mo Li, I-Chun Cheng
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. Asian Test Symposium 2009: 75-80 - [c17]Po-Juei Chen, James Chien-Mo Li, Hsing Jasmine Chao:
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects. Asian Test Symposium 2009: 349-354 - [c16]Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng:
BIST design optimization for large-scale embedded memory cores. ICCAD 2009: 197-200 - [c15]Bing-Chuan Bai
Power scan: DFT for power switches in VLSI designs. ITC 2009: 1 - [c14]Shiue-Tsung Shen, Wei-Hsiao Liu, Chien-Mo James Li, I-Chun Cheng
Very-Low-Voltage testing of amorphous silicon TFT circuits. ITC 2009: 1 - 2008
- [j11]Yu Huang, Ruifeng Guo
Survey of Scan Chain Diagnosis. IEEE Des. Test Comput. 25(3): 240-248 (2008) - [j10]H.-T. Lin, J. C.-M. Li:
Simultaneous capture and shift power reduction test pattern generator for scan testing. IET Comput. Digit. Tech. 2(2): 132-141 (2008) - [j9]Yu-Te Liaw, Bing-Chuan Bai, James Chien-Mo Li:
A Two-level Simultaneous Test Data and Time Reduction Technique for SOC. J. Inf. Sci. Eng. 24(3): 841-857 (2008) - [j8]Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li:
Diagnosis of Multiple Scan Chain Timing Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1104-1116 (2008) - [j7]James Chien-Mo Li, Po-Chou Lin, Chih-Ming Chiang, Chuo-Jan Pan, Chao-Wen Tseng:
Effective and Economic Phase Noise Testing for Single-Chip TV Tuners. IEEE Trans. Instrum. Meas. 57(10): 2265-2272 (2008) - [c13]Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte:
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151 - [c12]Geng-Ming Chiu, James Chien-Mo Li:
IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. ITC 2008: 1 - [c11]Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin, James Chien-Mo Li:
Diagnosis of Logic-to-chain Bridging Faults. ITC 2008: 1 - 2007
- [j6]Chun-Yi Lee
Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing. J. Low Power Electron. 3(2): 206-216 (2007) - [j5]James Chien-Mo Li, Hung-Mao Lin, Fang-Min Wang:
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis. IEEE Trans. Computers 56(3): 402-414 (2007) - [c10]Chun-Yi Lee
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. ASP-DAC 2007: 835-840 - 2006
- [c9]Yu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li:
Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis. ITC 2006: 1-9 - 2005
- [j4]James Chien-Mo Li:
Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1024-1030 (2005) - [j3]James Chien-Mo Li:
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains. IEEE Trans. Computers 54(11): 1467-1472 (2005) - [j2]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1748-1759 (2005) - [j1]James Chien-Mo Li:
Diagnosis of single stuck-at faults and multiple timing faults in scan chains. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 708-718 (2005) - [c8]Hung-Mao Lin, James Chien-Mo Li:
Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains. ITC 2005: 9 - [c7]Min-Hao Chiu, Chien-Mo James Li:
Jump Scan: A DFT Technique for Low Power Testing. VTS 2005: 277-282 - 2004
- [c6]Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra:
ELF-Murphy Data on Defects and Test Sets. VTS 2004: 16-22 - 2002
- [c5]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Sequence-Dependent Chips. VTS 2002: 187-192 - 2001
- [c4]Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Testing for resistive opens and stuck opens. ITC 2001: 1049-1058 - [c3]Chien-Mo James Li, Edward J. McCluskey:
Diagnosis of Tunneling Opens. VTS 2001: 22-27 - 2000
- [c2]Chien-Mo James Li, Edward J. McCluskey:
Testing for tunneling opens. ITC 2000: 85-94
1990 – 1999
- 1998
- [c1]Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. ITC 1998: 184-193
Coauthor Index
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