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Ting-Shuo Hsu
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2020 – today
- 2021
- [c13]Dun-An Yang, Yu-Teng Chang, Ting-Shuo Hsu, Jing-Jia Liou, Harry H. Chen:
ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph. ITC 2021: 10-19 - 2020
- [c12]Jiang-Tang Xiao, Ting-Shuo Hsu, Christian M. Fuchs, Yu-Teng Chang, Jing-Jia Liou, Harry H. Chen:
An ISA-level Accurate Fault Simulator for System-level Fault Analysis. ATS 2020: 1-6
2010 – 2019
- 2019
- [c11]Yi-Che Lee, Ting-Shuo Hsu, Chun-Tse Chen, Jing-Jia Liou, Juin-Ming Lu:
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators. VLSI-DAT 2019: 1-4 - 2017
- [c10]Zih-Huan Gao, Hau Hsu, Ting-Shuo Hsu, Jing-Jia Liou:
Post-Silicon Test Flow for Aging Prediction. ATS 2017: 70-75 - [c9]Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT 2017: 1-4 - 2015
- [c8]Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou:
Design of a scalable many-core processor for embedded applications. ASP-DAC 2015: 24-25 - [c7]Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, Jing-Jia Liou:
A fast and accurate network-on-chip timing simulator with a flit propagation model. ASP-DAC 2015: 797-802 - 2014
- [c6]Jiun-Yi Chiang, Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou:
Chip clustering with mutual information on multiple clock tests and its application to yield tuning. ICCD 2014: 243-248 - [c5]Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC 2014: 286-291 - 2013
- [c4]Shuo-You Hsu, Chih-Hsiang Hsu, Ting-Shuo Hsu, Jing-Jia Liou:
A Region-Based Framework for Design Feature Identification of Systematic Process Variations. Asian Test Symposium 2013: 265-270 - [c3]Jyu-Yuan Lai, Ting-Shuo Hsu, Po-Yu Chen, Chih-Tsun Huang, Yu-Hsun Chen, Jing-Jia Liou:
Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. MES 2013: 41-44 - 2012
- [c2]Jyu-Yuan Lai, Po-Yu Chen, Ting-Shuo Hsu, Chih-Tsun Huang, Jing-Jia Liou:
Design and analysis of a many-core processor architecture for multimedia applications. APSIPA 2012: 1-6 - [c1]Jun-Hua Kuo, Ting-Shuo Hsu, Jing-Jia Liou:
Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data. Asian Test Symposium 2012: 320-325
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