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ICICDT 2013: Pavia, Italy
- Proceedings of 2013 International Conference on IC Design & Technology, ICICDT 2013, Pavia, Italy, May 29-31, 2013. IEEE 2013, ISBN 978-1-4673-4740-2
- Dirk Wristers:
Complex trade-offs - Enablement of moore and more than moore. 1-2 - Bruno Murari:
Technology push or marketing pull? 3-4 - Marco D. Santambrogio
, Christian Pilato
The FASTER vision for designing dynamically reconfigurable systems. 5-8 - Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat:
An efficient metric of setup time for pulsed flip-flops based on output transition time. 9-12 - Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Balanced stochastic truncation of coupled 3D interconnect. 13-16 - Inhak Han, Youngsoo Shin:
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. 17-20 - Sandeep Miryala, Andrea Calimera
Exploration of different implementation styles for graphene-based reconfigurable gates. 21-24 - Antoine Litty, Sylvie Ortolland, Sorin Cristoloveanu, Helene Beckrich Ros, Dominique Golanski:
Improved modeling of isolated EDMOS in advanced CMOS technologies. 25-28 - Plamen Asenov, David New, Dave Reid, Campbell Millar, Scott Roy, Asen Asenov:
Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models. 29-32 - Worawit Somha, Hiroyuki Yamauchi
Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions. 33-36 - Marcello Calabrese, Carmine Miccoli, Christian Monzio Compagnoni, Luca Chiavarone, Silvia Beltrami, Andrea Parisi, Sebastiano Bartolone, Andrea L. Lacaita
Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology. 37-40 - Husni M. Habal, Helmut E. Graeb:
Evaluating analog circuit performance in light of MOSFET aging at different time scales. 41-44 - Joonho Kong, Sung Woo Chung:
Process variation-tolerant 3D microprocessor design: An efficient architectural solution. 45-48 - Guillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover
Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology. 53-56 - Dyuthi Kishan, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A capacitively coupled clock distribution network with correction for process dependent skew. 57-60 - Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. 61-64 - Kazuo Terada, Kazuhiko Sanai, Shouhei Matsuoka, Katsuhiro Tsuji:
Effective channel length of MOSFET with halo. 65-68 - Dina H. Triyoso
Impact of precursors choice on characteristics of PEALD SiN for spacer applications. 69-72 - Nguyen Dang Chien, Chun-Hsing Shih, Luu The Vinh
Quantum confinement effect in strained-Si1-xGex double-gate tunnel field-effect transistors. 73-76 - Alfonso Maurelli:
Status and perspectives of embedded Non-Volatile memories. 77-80 - Santhosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller:
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. 81-84 - Francesco Maria Puglisi
A compact model of hafnium-oxide-based resistive random access memory. 85-88 - Vivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy:
6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. 89-92 - Jan Ackaert, Aditi Malik, Daniel Vanderstraeten:
Impact of the leadframe profile on the occurrence of passivation cracks of plastic-encapsulated electronic power devices. 93-96 - Chih-Lin Chen, Yi-Lun Wu, Chun-Ying Juan, Chua-Chin Wang:
High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. 97-100 - Thuy Dao, Todd Roggenbauer, Gordon Boyd:
Improved deep trench isolation breakdown voltage for SmartMOS. 101-104 - Dario Bianchi, Fabio Quaglia, Andrea Mazzanti, Francesco Svelto:
High-voltage integrated Class-B amplifier for ultrasound transducers. 105-108 - Stephanie Simmons:
Silicon-based quantum computation. 109-114 - Faezeh Arab Hassani
Dual-gate junction-less FET-detection for in-plane nano-electro-mechanical resonators. 115-118 - Erika Covi
Automatic trimming procedure to enhance the accuracy of on-chip analog pulse generators. 119-122 - Sahel Abdinia, Daniele Raiteri, Stéphanie Jacob, Romain Coppard, Pieter van Lieshout, Giuseppe Palmisano, Antonino Scuderi, Arthur H. M. van Roermund, Eugenio Cantatore:
Analog to digital converters on plastic foils. 123-126 - Erika Covi
High-swing buffer for programmable resistive memories. 127-130 - Juanchi Wang, Marco Vacca, Mariagrazia Graziano, Massimo Ruo Roch
Biosequences analysis on NanoMagnet Logic. 131-134 - Andrea Baschirotto
Towards minimum power analog filters. 135-138 - Tommaso Vergine, Marcello De Matteis
A 32-channel 12-bits single slope A-to-D converter for LHC environment. 139-142 - Domenico M. Cavallo
A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology. 143-146 - Alessandro Pezzotta, Andrea Costantini, Marcello De Matteis
A low-power CMOS 0.13 µm Charge-Sensitive Preamplifier for GEM detectors. 147-150 - Davide Cartasegna, Piero Malcovati
Design of high-order class-D audio amplifiers. 151-154 - Chien-Hung Chen, Wei-Zen Chen:
A 10Bit, 10MS/s, low power cyclic ADC. 155-158 - Marcello De Matteis
A 34µW 75dB-dynamic-range CMOS analog front-end for intelligent tyre sensor network. 163-166 - Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
Breast cancer detection based on an UWB imaging system: Receiver design and simulations. 167-170 - Vincenzo Chironi, Stefano D'Amico
A dual-band balun LNA resilient to 5-6 GHz WLAN blockers for IR-UWB in 65nm CMOS. 171-174 - Anna Moroni, Danilo Manstretta
Design and modeling of passive mixer-first receivers for millimeter-wave applications. 175-178 - Hassan Gul, Alexander Simin:
Noise optimization of a broadband LNA for tuner applications. 179-182 - Cristian Andrei, Denis Raoulx, Guy Imbert, Bart Hovens, Andrea Scarpa:
Characterization and modeling of depletion-type nMOS transistors for RF switches with zero power consumption in ON-state. 183-186 - Akinobu Teramoto
High-speed and highly accurate evaluation of electrical characteristics in MOSFETs. 187-190 - Asahiko Matsuda
Atomistic simulations of plasma process-induced Si substrate damage - Effects of substrate bias-power frequency. 191-194 - Masamichi Suzuki, Atsuhiro Kinoshita, Yuichiro Mitani:
Improvement of gate disturb degradation in SONOS FETs for Vth mismatch compensation in CMOS analog circuits. 195-198 - Philippe Galy, T. Lim, Jean Jimenez, Boris Heitz, Ph. Benech, J. M. Fournier, D. Marin-Cudraz:
ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology. 199-202 - Ronald P. Luijten, Andreas C. Döring:
The DOME embedded 64 bit microserver demonstrator. 203-206 - Duc-Hung Le
A fast CAM-based Watermarking extraction on FPGA. 207-210 - Fabrizio Conso, Marco Grassi
I2C System-on-Chip for bi-dimensional gas-sensor arrays providing extended dynamic-range A/D conversion and row temperature regulation. 211-214 - Reeshav Kumar, Hrishikesh Deshpande, Gwan S. Choi, Alexander Sprintson
Bidirectional interconnect design for low latency high bandwidth NoC. 215-218 - Vinod Pangracious
TSV count minimization and thermal analysis for 3D Tree-based FPGA. 223-226 - Wenke Weinreich, Matthias Rudolph, Johannes Koch, Jan Paul, Konrad Seidel, Stefan Riedel, Jonas Sundqvist
High-density capacitors for SiP and SoC applications based on three-dimensional integrated metal-isolator-metal structures. 227-230 - Mariam Sadaka, Ionut Radu
Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration. 231-234 - Elisa Vianello, Olivier Thomas, M. Harrand, Santhosh Onkaraiah, T. Cabout, Boubacar Traore
Back-end 3D integration of HfO2-based RRAMs for low-voltage advanced IC digital design. 235-238
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