default search action
VLSI Circuits 2020: Honolulu, HI, USA
- IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020. IEEE 2020, ISBN 978-1-7281-9942-9
- Shourya Gupta, Daniel S. Truesdell, Benton H. Calhoun:
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes. 1-2 - Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo
, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. 1-2 - Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka:
A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. 1-2 - Pietro Caragiulo, Oscar Elisio Mattia, Amin Arbabian, Boris Murmann:
A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS. 1-2 - Lianbo Wu
A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain. 1-2 - Seokhyeon Jeong, Yejoong Kim, Gyouho Kim, David T. Blaauw:
A Pressure Sensing System with ±0.75 mmHg (3σ) Inaccuracy for Battery-Powered Low Power IoT Applications. 1-2 - Ibukunoluwa Momson, Shenggang Dong, Pavan Yelleswarapu, Wooyeol Choi, Kenneth K. O:
315-GHz Self-Synchronizing Minimum Shift Keying Receiver in 65-nm CMOS. 1-2 - Ji-Hun Lee, Gyeong-Gu Kang, Min-Woo Ko, Gyu-Hyeong Cho, Hyun-Sik Kim:
An 8Ω, 1.4W, 0.0024% THD+N Class-D Audio Amplifier with Bridge-Tied Load Half-Side Switching Mode Achieving Low Standby Quiescent Current of 660μA. 1-2 - Zheng Guo, Jami Wiedemer, Yusung Kim, Prithvee Sundararajan Ramamoorthy, Prateeksha Bindiganavile Sathyaprasad, Smita Shridharan, Daeyeon Kim, Eric Karl:
A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. 1-2 - Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn:
An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy. 1-2 - Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe
A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm. 1-2 - Anjana Dissanayake
A Multichannel, MEMS-Less -99dBm 260nW Bit-Level Duty Cycled Wakeup Receiver. 1-2 - Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun:
A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. 1-2 - Ming Ding, Minyoung Song
A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing. 1-2 - Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. 1-2 - Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen:
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. 1-2 - Ricardo Gomez Gomez, Edwige Bano, Andreia Cathelin, Sylvain Clerc:
A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI. 1-2 - Moon-Chul Choi
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. 1-2 - Christopher L. Ayala, Tomoyuki Tanaka, Ro Saito, Mai Nozoe, Naoki Takeuchi, Nobuyuki Yoshikawa:
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor using 1.4zJ/op Superconductor Josephson Junction Devices. 1-2 - Huajun Zhang
A -107.8 dB THD+N Low-EMI Multi-Level Class-D Audio Amplifier. 1-2 - Wei-Chih Chen, Chin-Hua Wen, Chin-Ming Fu, Tsung-Hsien Tsai, Yu-Chi Chen, Wen-Hung Huang, Chien-Chun Tsai, Alvin Leng Sun Loke, C. H. Kenny:
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. 1-2 - Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinmook Lee, Hoi-Jun Yoo:
A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping. 1-2 - Dzuhri Radityo Utomo, Dae-Woong Park, Byeonghun Yun, Sang-Gug Lee:
A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/-3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS. 1-2 - Kai Xing
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp. 1-2 - Dongyang Jiang
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. 1-2 - Masaru Osada, Zule Xu, Tetsuya Iizuka:
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. 1-2 - Sung-Jin Kim, Zachary Myers, Steven Herbst, ByongChan Lim, Mark Horowitz:
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator. 1-2 - Haidang Lin, Charles Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Nhat Nguyen, Shaishav Desai:
A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET. 1-2 - El Mehdi Boujamaa, Samsudeen Mohamed Ali, Steve Ngueya Wandji, Alexandra Gourio, Suk-Soo Pyo, Gwanhyeob Koh, Yoonjong Song, Taejoong Song, Jongwook Kye, Jean-Christophe Vial, Andrew Sowden, Manuj Rathor, Cyrille Dray:
A 14.7Mb/mm2 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference. 1-2 - Rohit Rothe, Sechang Oh, Kyojin David Choo, Seokhyeon Jeong, Minchang Cho, Dennis Sylvester, David T. Blaauw:
Sample and Average Common-Mode Feedback in a 101 nW Acoustic Amplifier. 1-2 - Yifan Lyu
A 1 GS/s Reconfigurable BW 2nd-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS. 1-2 - Xiaoliang Li
A Reconfigurable High-Bandwidth CMOS-MEMS Capacitive Accelerometer Array with High-g Measurement Capability and Low Bias Instability. 1-2 - Hyeongseok Seo
A 36-Channel SPAD-Integrated Scanning LiDAR Sensor with Multi-Event Histogramming TDC and Embedded Interference Filter. 1-2 - Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor. 1-2 - Hyochan An, Siddharth Venkatesan, Sam Schiferl, Tim Wesley, Qirui Zhang
A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge. 1-2 - Zhehong Wang, Ziyun Li, Li Xu
An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. 1-2 - Yunsup Lee, Andrew Waterman:
Managing Chip Design Complexity in the Domain-Specific SoC Era. 1-2 - Hoyoung Shin, Jisung Kim, Shinwuk Kang, Sungung Kwak:
A 28nm 10Mb Embedded Flash Memory for IoT Product with Ultra-Low Power Near-1V Supply Voltage and High Temperature for Grade 1 Operation. 1-2 - Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. 1-2 - Ali Nikoofard
A 920MHz 16-FSK Receiver Achieving a Sensitivity of -103dBm at 0.6mW Via an Integrated N-Path Filter Bank. 1-2 - Haoming Xin, Kevin Pelzers, Peter G. M. Baltus, Eugenio Cantatore, Pieter Harpe:
A 4.3fJ/Conversion-Step 6440μm2 All-Dynamic Capacitance-to-Digital Converter with Energy-Efficient Charge Reuse. 1-2 - Tae-Gyun Song, Dong-Kyu Kim, Jeong-Hyun Cho, Ji-Hun Lee, Hyun-Sik Kim
A 50.7dB-DR Finger-Resistance Extractable Multi-Touch Sensor IC Achieving Finger-Classification Accuracy of 97.7% on 6.7-Inch Capacitive Touch Screen Panel. 1-2 - Po-Han Peter Wang
A 4.4μW -92/-90.3dBm Sensitivity Dual-Mode BLE/Wi-Fi Wake-up Receiver. 1-2 - Tim Thielemans
A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency. 1-2 - Yang You, Glen A. Wiedemeier, Chad Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, Venkat Nammi, Jeffrey Okyere, Nathan Blanchard, Akil Sutton, Ze Zhang, David Friend, Diego Barba, Tyler Bohlke, Michael Spear, Vikram Raj, James Crugnale, Daniel Dreps, Pier Andrea Francese
A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS. 1-2 - Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. 1-2 - Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das:
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 7.1mW/mm2 Simultaneous Wireless Inter-Tier Data and Power Transfer. 1-2 - Jiannan Huang, Patrick P. Mercier
A -105dB THD 88dB-SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation. 1-2 - Koki Ishida, Masamitsu Tanaka
32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic. 1-2 - Zakir Zakir Ahmed, Harish K. Krishnamurthy, Sheldon Weng, Xiaosen Liu, Christopher Schaef, Nachiket V. Desai, Krishnan Ravichandran, James W. Tschanz, Vivek De:
An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering. 1-2 - Jeffrey Prinzie, Shuja Andrabi, Christophe Beghein, Changhua Cao, Xiaochuan Guo, Jon Strange, Bernard Tenbroek:
A Fast Locking 5.8 - 7.2 GHz Fractional-N Synthesizer with Sub-2 us Settling Time in 22 nm FDSOI. 1-2 - Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu:
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. 1-2 - Tuan Thanh Ta, Hiroshi Kubota, Koichi Kokubun, Toshiki Sugimoto, Masatoshi Hirono, Mitsuhiro Sengoku, Hisaaki Katagiri, Hidenori Okuni, Satoshi Kondo, Shinichi Ohtsuka, Honam Kwon, Keita Sasaki, Yutaka Ota, Kazuhiro Suzuki, Katsuyuki Kimura, Kentaro Yoshioka
A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR. 1-2 - Daniel S. Truesdell, Shuo Li, Benton H. Calhoun:
A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability using a Duty-Cycled Digital Frequency-Locked Loop. 1-2 - Jun Wang, Akshay Paul, Dinghong Zhang
1024-Electrode Hybrid Voltage/Current-Clamp Neural Interface System-on-Chip with Dynamic Incremental-SAR Acquisition. 1-2 - Giorgio Cristiano, Jiawei Liao, Alessandro Novello
A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops. 1-2 - Dong Yan, Dongsheng Brian Ma:
An Automotive-Use Battery-to-Load GaN-Based Power Converter with Anti-Aliasing Multi-Rate Spread-Spectrum Modulation and In-Cycle ZVS Switching. 1-2 - Jingcheng Wang, Hyochan An, Qirui Zhang
1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge Processors. 1-2 - Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun:
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. 1-2 - Loai G. Salem
An N-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting Achieving 13.9× Power Extraction Improvement. 1-2 - Matheus F. Pimenta, Çagri Gürleyük, Paul Walsh, Daniel O'Keeffe, Masoud Babaie, Kofi A. A. Makinwa:
A 200μW Eddy Current Displacement Sensor with 6.7nmRMS Resolution. 1-2 - Sangwook Han, Jaehyuk Jang, Jaeseung Lee, Daechul Jeong, Joonhee Lee, Jongsoo Lee, Chung Lau, Juyoung Han, Sung-Jun Lee, Jeongyeol Bae, Ikkyun Cho, Sang-Yun Lee, Shinwoong Kim, Jae Hoon Lee, Yanghoon Lee, Jaehong Jung
An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS. 1-2 - Arnaud Verdant, William Guicquero
A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition. 1-2 - Efraïm Eland, Shoubhik Karmakar, Burak Gönen, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
A 440μW, 109.8dB DR, 106.5dB SNDR Discrete-Time Zoom ADC with a 20kHz BW. 1-2 - Jaehong Jung
A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC. 1-2 - Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Kristof Vaesen, Piet Wambacq, Sang-Gug Lee:
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique. 1-2 - Yong-Un Jeong, Hyunkyu Park, Changho Hyun, Suhwan Kim:
A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces. 1-2 - Ibrahim Ahmed, Po-Wei Chiu, Chris H. Kim:
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems. 1-2 - Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. 1-2 - Jieqiong Du, Jia Zhou, Chia-Jen Liang, Boyu Hu, Yuan Du, Mau-Chung Frank Chang:
A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface. 1-2 - Ningyuan Cao, Baibhab Chatterjee
A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller. 1-2 - Xiaosen Liu, Harish K. Krishnamurthy, Claudia P. Barrera, Jing Han, Rajasekhara M. Narayana Bhatla, Scott Chiu, Khondker Zakir Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency. 1-2 - Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. 1-2 - Vikram B. Suresh, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew:
A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. 1-2 - Dongseok Im, Sanghoon Kang, Donghyeon Han, Sungpill Choi, Hoi-Jun Yoo:
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices. 1-2 - Wenda Zhao, Chanmin Park, Injun Park, Nan Sun, Youngcheol Chae:
An Always-on 4× Compressive VGA CMOS Imager with 51pJ/Pixel and >32dB PSNR. 1-2 - Longyang Lin, Saurabh Jain, Massimo Alioto:
Multi-Sensor Platform with Five-Order-of-Magnitude System Power Adaptation down to 3.1nW and Sustained Operation under Moonlight Harvesting. 1-2 - Peng Wang, Rishika Agarwala
A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. 1-2 - Hao Qiu, Toru Sai, Makoto Takamiya:
A 6.78 MHz Wireless Power Transfer System Enabling Perpendicular Wireless Powering with Efficiency Increase from 0.02% to 48.2% by Adaptive Magnetic Field Adder IC Integrating Shared Coupling Coefficient Sensor. 1-2 - Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew:
A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. 1-2 - Jan S. Rentmeister, M. Hassan Kiani, Kristofer S. J. Pister, Jason T. Stauth
A 120-330V, Sub-μA, 4-Channel Driver for Microrobotic Actuators with Wireless-Optical Power Delivery and over 99% Current Efficiency. 1-2 - Yong-Il Kwon, M. Kim, S. Park, M. Jeong, S. M. Lee, S. H. Lee, W. H. Lee, Yoon-Kyung Choi, Jin-Yup Lee:
A Low Noise Read-Out IC with Gate Driver for Full Front Display Area Optical Fingerprint Sensors. 1-2 - Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. 1-2 - Hung-Yi Huang, Xin-Yu Chen, Tai-Haur Kuo:
A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3. 1-2 - Yuri Kato, Yoshihisa Matoba, Katsumi Honda, Koji Ogawa, Kan Shimizu, Masataka Maehara, Atsushi Fujiwara, Aoi Odawara, Chigusa Yamane, Naohiko Kimizuka, Jun Ogi, Tadayuki Taura, Ikuro Suzuki, Yusuke Oike:
High-Density and Large-Scale MEA System Featuring 236, 880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis. 1-2 - Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. 1-2 - Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy:
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. 1-2 - Atsutake Kosuge, Takashi Oshima
A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems. 1-2 - Yuncheng Zhang
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. 1-2 - Hongseok Shin, Jinuk Kim, Doojin Jang, Donghee Cho, Yoontae Jung, Hyungjoo Cho, Unbong Lee, Chul Kim, Sohmyung Ha
A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero. 1-2 - Hsuan-Yu Chen, Wei-Tin Lin, Cheng-Hsiang Liao, Zong-Yi Lin, Zhi-Qiang Zhang, Yu-Yung Kao, Ke-Horng Chen
A Domino Bootstrapping 12V GaN Driver for Driving an On-Chip 650V eGaN Power Switch for 96% High Efficiency. 1-2 - Tengfei Chang, Timothy Claeys, Malisa Vucinic, Xavier Vilajosana, Titan Yuan, Brad Wheeler, Filip Maksimovic, David C. Burnett
Industrial IoT with Crystal-Free Mote-on-Chip. 1-2 - Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. 1-2 - Kwantae Kim
A 0.5V, 6.2μW, 0.059mm2 Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing. 1-2 - Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka:
A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit. 1-2 - Xiao Wu, Arun Subramaniyan, Zhehong Wang, Satish Narayanasamy
17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing. 1-2 - Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn:
A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, -0.12% for Battery Monitoring Applications. 1-2 - Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish Krishnamurthy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew:
A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. 1-2 - Jonathan E. Proesel, Nicolas Dupuis, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee:
A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS. 1-2 - Ivan Miro Panades, Benoît Tain
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. 1-2 - Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. 1-2 - Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. 1-2 - Chung-Cheng Chou, Zheng-Jun Lin, Chien-An Lai, Chin-I Su, Pei-Ling Tseng, Wei-Chi Chen, Wu-Chin Tsai, Wen-Ting Chu, Tong-Chern Ong, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. 1-2 - Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, Hoi-Jun Yoo, Joo-Young Kim:
Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision. 1-2 - Chieh-Fang Teng, Chun-Hsiang Chen, An-Yeu Andy Wu:
An Ultra-Low Latency 7.8-13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support. 1-2 - Yihan Zhang
A 0.72 nW, 1 Sample/s Fully Integrated pH Sensor with 65.8 LSB/pH Sensitivity. 1-2 - Sungjin Hong, Nan Sun:
A Portable NMR System with 50-kHz IF, 10-us Dead Time, and Frequency Tracking. 1-2 - Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu:
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. 1-2 - Chi-Chih Wen, Yu-Chi Lee, Yi-Chung Wu
A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems. 1-2 - Jang-Woo Lee, Dae-Hoon Na
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. 1-2 - Bogdan C. Raducanu, Samira Zali Asl, Stefano Stanzione, Chris van Liempd, Andrés Vásquez Quintero, Herbert De Smet
An Artificial Iris ASIC with High Voltage Liquid Crystal Driver, 10 nA Light Range Detector and 40 nA Blink Detector for LCD Flicker Removal. 1-2 - Chengjie Zhu, Yuhan Wen, Tao Liu, Haw Yang
A Packaged Ingestible Bio-Pill with 15-Pixel Multiplexed Fluorescence Nucleic-Acid Sensor and Bi-Directional Wireless Interface for In-Vivo Bio-Molecular Sensing. 1-2 - Dong-Ryeol Oh
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. 1-2 - Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. 1-2
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-17 20:47 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: