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Jinsu Lee
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2020 – today
- 2024
- [c24]Jinsu Lee, Keehoon Hong, Minsik Park:
Automotive Holographic Head-Up Display. SIGGRAPH Asia Posters 2024: 89:1-89:2 - 2023
- [j12]Dongseok Im
, Gwangtae Park
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC. IEEE J. Solid State Circuits 58(1): 177-188 (2023) - [j11]Dongseok Im
A Mobile 3-D Object Recognition Processor With Deep-Learning-Based Monocular Depth Estimation. IEEE Micro 43(3): 74-82 (2023) - 2022
- [c23]Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li
A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms. COOL CHIPS 2022: 1-3 - [c22]Dongseok Im, Gwangtae Park, Zhiyong Li
DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip. HCS 2022: 1-25 - [c21]Dongseok Im, Gwangtae Park, Zhiyong Li
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms. ISSCC 2022: 510-512 - 2021
- [j10]Ji-Hoon Kim
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. IEEE J. Solid State Circuits 56(4): 1093-1104 (2021) - [j9]Donghyeon Han
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning. IEEE J. Solid State Circuits 56(5): 1630-1640 (2021) - [c20]Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo:
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. HCS 2021: 1-20 - [c19]Zhiyong Li
A 3.6 TOPS/W Hybrid FP-FXP Deep Learning Processor with Outlier Compensation for Image-to-Image Application. ISCAS 2021: 1-5 - [c18]Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, Hoi-Jun Yoo:
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. VLSI Circuits 2021: 1-2 - [c17]Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo:
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer. VLSI Circuits 2021: 1-2 - 2020
- [j8]Juhyoung Lee
SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 320-334 (2020) - [j7]Sangyeob Kim
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1181-1193 (2020) - [j6]Jinsu Lee
The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices. IEEE Trans. Circuits Syst. 67-I(10): 3458-3470 (2020) - [c16]Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, Hoi-Jun Yoo, Joo-Young Kim:
Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j5]Donghyeon Han
A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(5): 1794-1804 (2019) - [c15]Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinsu Lee, Hoi-Jun Yoo:
A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices. ISCAS 2019: 1-5 - [c14]Jinsu Lee, Juhyoung Lee, Donghyeon Han, Jinmook Lee, Gwangtae Park, Hoi-Jun Yoo:
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16. ISSCC 2019: 142-144 - [c13]Juhyoung Lee, Dongjoo Shin, Jinsu Lee, Jinmook Lee, Sanghoon Kang, Hoi-Jun Yoo:
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices. VLSI Circuits 2019: 302- - [c12]Donghyeon Han, Jinsu Lee, Jinmook Lee, Hoi-Jun Yoo:
A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture. VLSI Circuits 2019: 304- - 2018
- [j4]Dongjoo Shin, Jinmook Lee, Jinsu Lee, Juhyoung Lee, Hoi-Jun Yoo:
DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture. IEEE Micro 38(5): 85-93 (2018) - [j3]Youchang Kim
A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 567-580 (2018) - [c11]Hwa-Yeon Kim, Jinsu Lee, Na Young Yeo, Marcella Astrid, Seung-Ik Lee, Young-Kil Kim:
CNN based Sentence Classification with Semantic Features using Word Clustering. ICTC 2018: 484-488 - [c10]Jinsu Lee, Sang-Kwang Lee, Seong-Il Yang:
An Ensemble Method of CNN Models for Object Detection. ICTC 2018: 898-901 - [c9]Donghyeon Han, Jinsu Lee, Jinmook Lee, Sungpill Choi, Hoi-Jun Yoo:
A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices. ISCAS 2018: 1-5 - [c8]Sungpill Choi, Jinsu Lee, Kyuho Jason Lee
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices. ISSCC 2018: 220-222 - 2017
- [j2]Youchang Kim, Dongjoo Shin, Jinsu Lee, Hoi-Jun Yoo:
BRAIN: A Low-Power Deep Search Engine for Autonomous Robots. IEEE Micro 37(5): 11-19 (2017) - [j1]Jinsu Lee
A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2714-2723 (2017) - [c7]Dongjoo Shin, Jinmook Lee, Jinsu Lee, Juhyoung Lee, Hoi-Jun Yoo:
An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks. COOL Chips 2017: 1-2 - [c6]Jinsu Lee, Junseong Bang, Seong-Il Yang:
Object detection with sliding window in images including multiple similar objects. ICTC 2017: 803-806 - [c5]Dongjoo Shin, Jinmook Lee, Jinsu Lee, Hoi-Jun Yoo:
14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks. ISSCC 2017: 240-241 - 2016
- [c4]Youchang Kim
A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots. COOL Chips 2016: 1-2 - [c3]Qiongjie Lin, Jinsu Lee, Mary Ann Weitnauer:
Practical Residual Error of Interference Cancellation for Spread MSK with a Pseudo-Noise Preamble. GLOBECOM 2016: 1-6 - [c2]Jinsu Lee, Dongjoo Shin, Youchang Kim
A 17.5 fJ/bit energy-efficient analog SRAM for mixed-signal processing. ISCAS 2016: 1010-1013 - [c1]Youchang Kim
14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robots. ISSCC 2016: 258-259 - [i1]Zahra Khatami, Sungpack Hong, Jinsu Lee, Siegfried Depner, Hassan Chafi:
A Balanced Parallel Distributed Sorting Implemented with PGX.D. CoRR abs/1611.00463 (2016)
Coauthor Index
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last updated on 2024-12-08 01:31 CET by the dblp team
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