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Han-Gon Ko
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2020 – today
- 2024
- [j17]Dongwoo Kang, Han-Gon Ko
, Kwanseo Park
A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4633-4637 (2024) - 2023
- [c14]Jung-Hun Park, Hyeonseok Lee, Hoyeon Cho, Sanghee Lee, Kwang-Hoon Lee, Han-Gon Ko, Deog-Kyoon Jeong:
A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. ISSCC 2023: 410-411 - 2022
- [j16]Kwanseo Park
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. IEEE J. Solid State Circuits 57(2): 573-585 (2022) - [j15]Yeonggeun Song
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 759-763 (2022) - [c13]Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong:
A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC 2022: 249-252 - [c12]Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong:
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. VLSI Technology and Circuits 2022: 150-151 - 2021
- [j14]Byungjun Kang
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. IEEE Access 9: 156789-156798 (2021) - [j13]Min-Seong Choo
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021) - [j12]Chang-Soo Yoon, Han-Gon Ko
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 136-140 (2021) - [c11]Woonghee Lee, Minkyo Shim, Yunhee Lee
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC 2021: 475-478 - 2020
- [j11]Sangyoon Lee
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020) - [j10]Soyeong Shin
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1814-1818 (2020) - [j9]Chan-Ho Kye, Han-Gon Ko
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1099-1106 (2020) - [j8]Hye-Yoon Joo
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2708-2720 (2020) - [c10]Kwanseo Park, Minkyo Shim, Han-Gon Ko, Deog-Kyoon Jeong:
6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. ISSCC 2020: 124-126 - [c9]Han-Gon Ko, Soyeong Shin
6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. ISSCC 2020: 128-130 - [c8]Soyeong Shin
22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. ISSCC 2020: 340-342 - [c7]Moon-Chul Choi
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j7]Han-Gon Ko
Reference Spur Reduction Techniques for a Phase-Locked Loop. IEEE Access 7: 38035-38043 (2019) - [j6]Min-Seong Choo
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. IEEE J. Solid State Circuits 54(10): 2812-2822 (2019) - [j5]Moon-Chul Choi
A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1927-1931 (2019) - [j4]Min-Seong Choo
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1932-1936 (2019) - [c6]Moon-Chul Choi, Haram Ju, Han-Gon Ko, Deog-Kyoon Jeong:
A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. ICEIC 2019: 1-4 - [c5]Han-Gon Ko, Soyeong Shin
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits 2019: 94- - 2018
- [j3]Sung-Yong Cho
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - [j2]Gyu-Seob Jeong
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1395-1399 (2018) - [j1]Min-Seong Choo
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1819-1823 (2018) - [c4]Min-Seong Choo
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. A-SSCC 2018: 73-76 - 2017
- [c3]Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC 2017: 494-495 - 2016
- [c2]Jinhyung Lee, Sungwoo Kim, Min-Seong Choo
A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS 2016: 1662-1665 - 2015
- [c1]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC 2015: 384-387
Coauthor Index
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