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Silvia M. Müller
Silvia Melitta Müller – Silvia M. Mueller
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2020 – today
- 2024
- [i2]Lucas M. Dutton, Christopher Kumar Anand
, Robert F. Enenkel, Silvia Melitta Müller:
Inexactness and Correction of Floating-Point Reciprocal, Division and Square Root. CoRR abs/2404.00387 (2024) - 2023
- [c27]Lucas M. Dutton, Christopher K. Anand, Robert F. Enenkel, Silvia Melitta Müller:
Optimized Circuit to Correct Outliers in Floating-Point Functions. CASCON 2023: 94-102 - 2022
- [j11]Sae Kyu Lee
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits 57(1): 182-197 (2022) - [j10]Riduan Khaddam-Aljameh
HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs. IEEE J. Solid State Circuits 57(4): 1027-1038 (2022) - [i1]Manuel Le Gallo, Riduan Khaddam-Aljameh, Milos Stanisavljevic, Athanasios Vasilopoulos, Benedikt Kersting, Martino Dazzi, Geethan Karunaratne, Matthias Braendli
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. CoRR abs/2212.02872 (2022) - 2021
- [c26]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - [c25]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - [c24]Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC 2021: 144-146 - [c23]Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing. VLSI Circuits 2021: 1-2 - 2020
- [j9]Anthony Saporito, Martin Recktenwald, Christian Jacobi, Gerrit Koch, Deanna Postles Dunn Berger, Robert J. Sonnelitter, Craig R. Walters
Design of the IBM z15 microprocessor. IBM J. Res. Dev. 64(5/6): 7:1-7:18 (2020) - [j8]Swagath Venkataramani
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108(12): 2232-2250 (2020) - [c22]Robert F. Enenkel, Silvia M. Müller, Christopher K. Anand:
Novel hardware & software design for mathematical and AI acceleration. CASCON 2020: 268-269 - [c21]Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c20]Ankur Agrawal, Bruce M. Fleischer, Silvia M. Mueller, Xiao Sun
DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference. ARITH 2019: 92-95 - 2018
- [c19]Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
Across the Stack Opportunities for Deep Learning Acceleration. ISLPED 2018: 35:1-35:2 - [c18]Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits 2018: 35-36 - 2016
- [c17]Cédric Lichtenau, Steven R. Carlough, Silvia Melitta Müller:
Quad Precision Floating Point on the IBM z13. ARITH 2016: 87-94 - 2014
- [b4]Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul:
A Pipelined Multi-core MIPS Machine - Hardware Implementation and Correctness Proof. Lecture Notes in Computer Science 9000, Springer 2014, ISBN 978-3-319-13905-0, pp. 1-344 - [c16]Vikas Chandra, Subhasish Mitra, Chen-Yong Cher, Silvia Melitta Müller:
Cross layer resiliency in real world. DATE 2014: 1 - 2011
- [c15]Maarten Boersma, Michael Kroener, Christophe Layer, Petra Leber, Silvia M. Müller, Kerstin Schelm:
The POWER7 Binary Floating-Point Unit. IEEE Symposium on Computer Arithmetic 2011: 87-91 - [c14]Steven R. Carlough, Adam Collura, Silvia M. Müller, Michael Kroener:
The IBM zEnterprise-196 Decimal Floating-Point Accelerator. IEEE Symposium on Computer Arithmetic 2011: 139-146
2000 – 2009
- 2009
- [c13]Jochen Preiss, Maarten Boersma, Silvia Melitta Müller:
Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units. IEEE Symposium on Computer Arithmetic 2009: 48-56 - 2007
- [j7]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - [j6]Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough:
IBM POWER6 accelerators: VMX and DFU. IBM J. Res. Dev. 51(6): 663-684 (2007) - 2006
- [j5]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - [j4]Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong:
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. IEEE J. Solid State Circuits 41(4): 759-771 (2006) - 2005
- [c12]Roger A. Golliver, Silvia M. Müller, Stuart F. Oberman, Martin S. Schmookler, Debjit Das Sarma, Andrew Beaumont-Smith:
Pain versus Gain in the Hardware Design of FPUs and Supercomputers. IEEE Symposium on Computer Arithmetic 2005: 39 - [c11]Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong:
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. IEEE Symposium on Computer Arithmetic 2005: 59-67 - 2000
- [b3]Silvia M. Müller, Wolfgang J. Paul:
Computer architecture - complexity and correctness. Springer 2000, ISBN 978-3-540-67481-8, pp. I-XIII, 1-553 - [j3]Guy Even, Silvia M. Müller, Peter-Michael Seidel:
A dual precision IEEE floating-point multiplier. Integr. 29(2): 167-180 (2000) - [c10]Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis:
Parallel Computer Architecture. Euro-Par 2000: 537-538 - [c9]Daniel Kröning, Wolfgang J. Paul, Silvia M. Müller:
Proving the Correctness of Pipelined Micro-Architectures. MBMV 2000: 89-98
1990 – 1999
- 1999
- [c8]Silvia M. Müller:
A Hardware Scheduler for Controlling Variable Latency Functional Units. Applied Informatics 1999: 581-583 - [c7]Silvia M. Müller, Holger W. Leister, Peter Dell, Nikolaus Gerteis, Daniel Kroening:
The Impact of Hardware Scheduling Mechanismus on the Performance and Cost of Processor Designs. ARCS 1999: 65-73 - [c6]Silvia M. Müller:
On the Scheduling of Variable Latency Functional Units. SPAA 1999: 148-154 - 1998
- [j2]Silvia M. Müller, Wolfgang J. Paul:
On the Correctness of Hardware Scheduling Mechanisms for Out-of-Order Execution. J. Circuits Syst. Comput. 8(2): 301-314 (1998) - 1997
- [c5]Silvia M. Müller, Uzi Vishkin:
Conflict-Free Access to Multiple Single-Ported Register Files. IPPS 1997: 672-678 - 1996
- [c4]Silvia M. Müller, Wolfgang J. Paul:
Making the Original Scoreboard Mechanism Deadlock Free. ISTCS 1996: 92-99 - 1995
- [b2]Silvia M. Müller, Wolfgang J. Paul:
The Complexity of Simple Computer Architectures. Lecture Notes in Computer Science 995, Springer 1995, ISBN 3-540-60580-0 - 1994
- [c3]Silvia M. Müller, Benedict Gomes:
Efficient mapping of randomly sparse neural networks on parallel vector supercomputers. SPDP 1994: 170-177 - [p1]Arno Formella, Silvia M. Müller, Wolfgang J. Paul, Anke Bingert:
Isolating the Reasons for the Performance of Parallel Machines on Numerical Programs. Automatic Parallelization 1994: 45-77 - 1991
- [b1]Silvia Melitta Müller:
RISC und CISC: Optimierung und Vergleich von Architekturen. Saarland University, Saarbrücken, Germany, 1991, pp. 1-377 - [j1]Silvia M. Müller, Dieter Scheerer:
A method to parallelize tridiagonal solvers. Parallel Comput. 17(2-3): 181-188 (1991)
1980 – 1989
- 1989
- [c2]Silvia M. Müller, Wolfgang J. Paul:
Contributions of Theoretical Computer Science, Applied Computer Science and Numerical Mathematics to the Design of Parallel Computers. IFIP Congress 1989: 459-460 - 1988
- [c1]P. Bergmann, Jörg Keller, Thomas Malter, Silvia M. Müller, Wolfgang J. Paul, Thorsten Pöschel, O. Schlüter, Lothar Thiele:
Implementierung eines informationstheoretischen Ansatzes zur Bilderkennung. Innovative Informations-Infrastrukturen 1988: 187-197
Coauthor Index
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last updated on 2024-10-07 21:20 CEST by the dblp team
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