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Yi Shen 0007
Person information
- affiliation: Xidian University, School of Microelectronics, Xi'an, China
Other persons with the same name
- Yi Shen — disambiguation page
- Yi Shen 0001
— Harbin Institute of Technology, Department of Control Science and Engineering, Harbin, China
- Yi Shen 0002 — Huazhong University of Science and Technology, Department of Control Science and Engineering, Wuhan, China
- Yi Shen 0003
- Yi Shen 0004
- Yi Shen 0005 — University of North Carolina, Charlotte, NC, USA
- Yi Shen 0006
- Yi Shen 0008
- Yi Shen 0009
- Yi Shen 0011
- Yi Shen 0012 — Zhejiang University, College of Computer Science and Technology, Hangzhou, China
- Yi Shen 0013
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2020 – today
- 2024
- [j30]Yun Li, Yi Shen, Yue Cao, Mengtong Wu, Li Dang, Shubin Liu, Ruixue Ding, Zhangming Zhu:
Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS. Microelectron. J. 151: 106340 (2024) - [j29]Haolin Han
A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique. Microelectron. J. 151: 106352 (2024) - [j28]Haolin Han
A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry. Microelectron. J. 153: 106432 (2024) - [j27]Li Dang
A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1061-1070 (2024) - [j26]Haolin Han
A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1495-1505 (2024) - [j25]Yuke Shen
A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 3951-3960 (2024) - [j24]Junyan Hao, Yi Shen, Jin Zhang
A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 16-20 (2024) - [j23]Hongzhi Liang
A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 81-85 (2024) - [j22]Dengquan Li
A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm. IEEE Trans. Instrum. Meas. 73: 1-10 (2024) - [j21]Dengquan Li
A Wideband Input Buffer Based on Cascade Complementary Source Follower. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 962-966 (2024) - 2023
- [j20]Junyan Hao, Yi Shen, Angyang Li, Min Wang, Qing Zou, Zheng Qiu, Shubin Liu, Zhangming Zhu:
An offset and gain error calibration method in high-precision SAR ADCs. Microelectron. J. 139: 105915 (2023) - [j19]Yi Shen
An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 166-175 (2023) - [j18]Xin Xin
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2293-2305 (2023) - [j17]Dengquan Li
A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3557-3566 (2023) - [j16]Yi Shen
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1870-1873 (2023) - [j15]Xin Zhao
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2147-2151 (2023) - [c8]Hongzhi Liang, Yi Shen, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step. A-SSCC 2023: 1-3 - [c7]Yuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen, Ruixue Ding, Zhangming Zhu:
A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping. A-SSCC 2023: 1-3 - [c6]Yi Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. CICC 2023: 1-2 - 2022
- [j14]Jiale Ding, Yukai Huang, Dengquan Li
Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs. Circuits Syst. Signal Process. 41(12): 6632-6650 (2022) - [j13]Yukai Huang, Jiale Ding, Dengquan Li
A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration. Microelectron. J. 122: 105394 (2022) - [j12]Xiyuan Tang
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2249-2262 (2022) - [j11]Yi Shen
A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3965-3975 (2022) - [j10]Dengquan Li
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1558-1562 (2022) - [c5]Tian Feng, Dengquan Li, Jiale Ding, Shubin Liu, Yi Shen, Zhangming Zhu:
A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower. ICTA 2022: 13-14 - 2020
- [j9]Yi Shen
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits 55(3): 680-692 (2020) - [j8]Shubin Liu, Haolin Han, Yi Shen, Zhangming Zhu
A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2602-2611 (2020) - [c4]Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun:
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC 2020: 1-4 - [c3]Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun:
A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j7]Linxiao Shen
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54(12): 3375-3385 (2019) - [c2]Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC 2019: 1-4 - [c1]Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun:
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. ISSCC 2019: 64-66 - 2018
- [j6]Yi Shen, Zhangming Zhu
A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 51-60 (2018) - [j5]Jingyu Wang
Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2378-2388 (2018) - 2016
- [j4]Yi Shen, Zhangming Zhu:
Analysis and optimization of the two-stage pipelined SAR ADCs. Microelectron. J. 47: 40-44 (2016) - [j3]Yi Shen, Shubin Liu, Zhangming Zhu:
A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS. Microelectron. J. 57: 26-33 (2016) - [j2]Shubin Liu, Yi Shen, Zhangming Zhu
A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1616-1627 (2016) - 2014
- [j1]Zhangming Zhu, Zheng Qiu, Yi Shen, Yintang Yang:
A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor. IET Circuits Devices Syst. 8(6): 427-434 (2014)
Coauthor Index
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