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Muya Chang
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- affiliation: Purdue University, West Lafayette, IN, USA
- affiliation (PhD 2020): Georgia Institute of Technology, Atlanta, GA, USA
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2020 – today
- 2024
- [j10]Ashwin Sanjay Lele
, Muya Chang
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59(1): 52-64 (2024) - [j9]Nealson Li
E-Gaze: Gaze Estimation With Event Camera. IEEE Trans. Pattern Anal. Mach. Intell. 46(7): 4796-4811 (2024) - [j8]Steven Davis
In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2538-2549 (2024) - [c21]Kaushik Bhattacharyya, Minxiang Gong, Muya Chang, Xin Zhang, Arijit Raychowdhury:
A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC. ISCAS 2024: 1-5 - [c20]Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC 2024: 482-484 - [c19]Brian Crafton, Samuel D. Spetalnick, Muya Chang, Arijit Raychowdhury:
A 28nm Approximate / Binary 6T CAM for Sequence Alignment. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c18]Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. CICC 2023: 1-2 - [c17]Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Arijit Raychowdhury, Yan Fang:
Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem. DAC 2023: 1-6 - [c16]Jianbo Liu, Boyang Cheng
Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing. DATE 2023: 1-6 - [c15]Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury:
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking. ISCAS 2023: 1 - [c14]Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC 2023: 426-427 - [c13]Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j7]Jong-Hyeok Yoon
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE J. Solid State Circuits 57(1): 68-79 (2022) - [j6]Jong-Hyeok Yoon
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE J. Solid State Circuits 57(3): 845-857 (2022) - [j5]Ningyuan Cao
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller. IEEE J. Solid State Circuits 57(8): 2545-2559 (2022) - [c12]Muya Chang, Xunzhao Yin, Zoltán Toroczkai, Xiaobo Hu, Arijit Raychowdhury:
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems. CICC 2022: 1-2 - [c11]Ningyuan Cao, Jianbo Liu, Boyang Cheng
Stochastic Mixed-Signal Circuit Design for In-Sensor Privacy. ICCAD 2022: 11:1-11:9 - [c10]Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC 2022: 1-3 - [c9]Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. ISSCC 2022: 1-3 - 2021
- [b1]Muya Chang:
Hardware Dynamical System for Solving Optimization Problems. Georgia Institute of Technology, Atlanta, GA, USA, 2021 - [j4]Debayan Das
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. IEEE J. Solid State Circuits 56(1): 136-150 (2021) - [j3]Minxiang Gong
A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1408-1412 (2021) - [c8]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. CICC 2021: 1-2 - [c7]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. ISSCC 2021: 404-406 - 2020
- [j2]Ningyuan Cao
A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics. IEEE J. Solid State Circuits 55(1): 49-59 (2020) - [j1]Muya Chang
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers. IEEE J. Solid State Circuits 55(3): 629-638 (2020) - [c6]Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. ISSCC 2020: 424-426 - [c5]Ningyuan Cao, Baibhab Chatterjee
A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c4]Muya Chang, Li-Hsiang Lin
Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations. CICC 2019: 1-4 - [c3]Muya Chang, Samantak Gangopadhyay, Tomer Hamam, Justin Romberg, Arijit Raychowdhury:
Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture. ICASSP 2019: 1493-1497 - [c2]Ningyuan Cao, Muya Chang, Arijit Raychowdhury:
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics. ISSCC 2019: 222-224 - 2018
- [c1]Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. DRC 2018: 1-2
Coauthor Index
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last updated on 2024-10-18 19:25 CEST by the dblp team
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