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3DIC 2013: San Francisco, CA, USA
- 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013. IEEE 2013, ISBN 978-1-4673-6484-3
- Takafumi Fukushima
, Jichoel Bea, Mariappan Murugesan, Ho-Young Son
3D memory chip stacking by multi-layer self-assembly technology. 1-4 - Takafumi Fukushima
Development of via-last 3D integration technologies using a new temporary adhesive system. 1-4 - Tadao Nakamura, Yoriko Mizushima, Hideki Kitada, Young-Suk Kim, Nobuhide Maeda, Shoichi Kodama, Ryuichi Sugie
Influence of wafer thinning process on backside damage in 3D integration. 1-6 - Zvi Or-Bach:
The monolithic 3D advantage: Monolithic 3D is far more than just an alternative to 0.7x scaling. 1-7 - Kaushik Ghosh, C. C. Yap, Beng Kang Tay
Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges. 1-4 - Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri
Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. 1-6 - Yann Civale, Herman Meynen, Ranjith S. E. John, Peng-Fei Fu, Craig R. Yeakle, Sheng Wang, Stefan Krausse, Thomas Rapps, Stefan Lutter:
Cost-effective temporary bonding and debonding material solution towards high-volume manufacturing 2.5D/3D through-silicon via integrated circuits. 1-5 - Yuri Sylvester, Luke Hunter, Bruce Johnson, Raleigh Estrada:
3D X-ray microscopy: A near-SEM non-destructive imaging technology used in the development of 3D IC packaging. 1-7 - Akihiro Ikeda, L. J. Qiu, K. Nakahara, Tanemasa Asano:
Surface passivation of Cu cone bump by self-assembled-monolayer for room temperature Cu-Cu bonding. 1-4 - Jun-Yeob Song, Jae Hak Lee, Hyoung Joon Kim, Chang Woo Lee, Tae Ho Ha:
High reliability insert-bump bonding process for 3D integration. 1-4 - Stephen H. Pan, Norman Chang, Tadaaki Hitomi:
3D-IC dynamic thermal analysis with hierarchical and configurable chip thermal model. 1-8 - Jae Hak Lee, Hyoung Joon Kim, Jun-Yeob Song, Chang Woo Lee, Tae Ho Ha:
A study on wafer level TSV build-up integration method. 1-4 - Yassir Madhour, Michael Zervas, Gerd Schlottig, Thomas Brunschwiler, Yusuf Leblebici, John Richard Thome, Bruno Michel:
Integration of intra chip stack fluidic cooling using thin-layer solder bonding. 1-8 - Mariappan Murugesan, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. 1-4 - Y. Lamy, Laurent Dussopt, Ossama El Bouayadi
A compact 3D silicon interposer package with integrated antenna for 60GHz wireless applications. 1-6 - Heegon Kim, Jonghyun Cho, Jonghoon J. Kim, Daniel H. Jung, Sumin Choi, Joungho Kim, Junho Lee, Kunwoo Park:
Eye-diagram simulation and analysis of a high-speed TSV-based channel. 1-7 - Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. 1-5 - Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 1-7 - Daniel H. Jung, Jonghyun Cho, Heegon Kim, Jonghoon J. Kim, Hongseok Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi:
Fault isolation of short defect in through silicon via (TSV) based 3D-IC. 1-4 - Melanie Brocard, Cédric Bermond, Thierry Lacrevaz, Alexis Farcy, Patrick Le Maitre, P. Scheer, Patrick Leduc, Séverine Cheramy, Bernard Fléchet:
RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits. 1-8 - Yann Beilliard
Chip to wafer copper direct bonding electrical characterization and thermal cycling. 1-7 - Kouji Kiyoyama, Y. Sato, Hiroyuki Hashimoto, Kang Wook Lee, Takafumi Fukushima
A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. 1-4 - Ricardo I. Fuentes:
Wafer thinning for 3D integration. 1-5 - Katsuya Kikuchi, Fumiki Kato
Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. 1-4 - Zhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty
Face-to-face bus design with built-in self-test in 3D ICs. 1-7 - Edward J. Suh, Paul D. Franzon
Design of 60 GHz contactless probe system for RDL in passive silicon interposer. 1-5 - Jonghoon J. Kim, Heegon Kim, Sukjin Kim, Bumhee Bae, Daniel H. Jung, Sunkyu Kong, Joungho Kim, Junho Lee, Kunwoo Park:
Non-contact wafer-level TSV connectivity test methodology using magnetic coupling. 1-4 - Laura B. Mauer, John Taddei, Elena Lawrence, Ramey Youssef, Stephen P. Olson:
Silicon Etch with integrated metrology for through silicon via (TSV) reveal. 1-4 - Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen
Si interposer build-up options and impact on 3D system cost. 1-5 - Nahid M. Hossain, MunEm Hossain, Abdul Hamid Bin Yousuf, Masud H. Chowdhury:
Thermal aware Graphene based Through Silicon Via design for 3D IC. 1-4 - Jiacheng Wang, Shunli Ma, Sai Manoj Pudukotai Dinakarrao
High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. 1-4 - Zhenqian Zhang, Paul D. Franzon
TSV-based, modular and collision detectable face-to-back shared bus design. 1-5 - Indira Rawat, M. K. Gupta, Virendra Singh:
Thermal analysis and modeling of 3D integrated circuits for test scheduling. 1-5 - Cristiano Santos, Pascal Vivet
System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit. 1-6 - Matthew Lueck, Chris W. Gregory, Dean Malta, Alan Huffman, John M. Lannon, Dorota Temple:
High density interconnect bonding of heterogeneous materials using non-collapsible microbumps at 10 μm pitch. 1-5 - Thomas Uhrmann, Thorsten Matthias, Markus Wimplinger, Jurgen Burggraf, Daniel Burgstaller, Harald Wiesbauer, Paul Lindner:
Recent progress in thin wafer processing. 1-8 - Shreepad Panth, Kambiz Samadi, Sung Kyu Lim
Test-TSV estimation during 3D-IC partitioning. 1-7 - Papa Momar Souare, François de Crecy, Vincent Fiori, M. Haykel Ben Jamaa, Alexis Farcy, Sébastien Gallois-Garreignot, Andras Borbely, Jean-Philippe Colonna, Perceval Coudrain
Thermal correlation between measurements and FEM simulations in 3D ICs. 1-6 - Kentaro Mori, Yoshihiro Ono, Shinji Watanabe, Toshikazu Ishikawa, Michiaki Sugiyama, Satoshi Imasu, Toshihiko Ochiai, Ryo Mori, Tsuyoshi Kida, Tomoaki Hashimoto, Hideki Tanaka, Michitaka Kimura:
High density and reliable packaging technology with Non Conductive Film for 3D/TSV. 1-7 - Erfan Azarkhish, Igor Loi, Luca Benini
A high-performance multiported L2 memory IP for scalable three-dimensional integration. 1-8 - Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen
Low temperature (<180 °C) bonding for 3D integration. 1-5 - Valerio Re
Active pixel sensors with enhanced pixel-level analog and digital functionalities in a 2-tier 3D CMOS technology. 1-7 - Ryusuke Egawa, Masayuki Sato
Vertically integrated processor and memory module design for vector supercomputers. 1-6 - Bipin Rajendran
Pulsed laser annealing: A scalable and practical technology for monolithic 3D IC. 1-5 - Jui-Chin Chen, John H. Lau, Tzu-Chien Hsu, Chien-Chou Chen, Pei-Jer Tzeng, Po-Chih Chang, Chun-Hsien Chien, Yiu-Hsiang Chang, Shang-Chun Chen, Yu-Chen Hsin, Sue-Chen Liao, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao:
Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer. 1-5 - Vinod Pangracious
Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. 1-8 - Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi:
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 1-5 - Keiji Matsumoto, Soichiro Ibaraki, Kuniaki Sueoka, Katsuyuki Sakuma
Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack. 1-8 - Jason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb:
Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination. 1-6 - Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 1-4 - Caleb Serafy, Bing Shi, Ankur Srivastava
High performance 3D stacked DRAM processor architectures with micro-fluidic cooling. 1-8 - Yue Zhang, Hanju Oh, Muhannad S. Bakir:
Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs. 1-6 - Tiantao Lu, Ankur Srivastava
Detailed electrical and reliability study of tapered TSVs. 1-7 - Neela Gopi, Jeffrey Draper:
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC. 1-6 - Hong-Yeol Lim, Min-Kwan Kee, Gi-Ho Park:
Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits. 1-5 - Leonid Yavits, Amir Morad, Ran Ginosar:
3D cache hierarchy optimization. 1-5 - Benjamin Vianne, Pierre Bar, Vincent Fiori, Sebastien Petitdidier, Norbert Chevrier, Sébastien Gallois-Garreignot, Alexis Farcy, Pascal Chausse, Stephanie Escoubas, Nicolas Hotellier, Olivier Thomas:
Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments. 1-7 - Jubee Tada, Ryusuke Egawa, Hiroaki Kobayashi:
Design of a 3-D stacked floating-point adder. 1-4 - Paul D. Franzon
Thermal requirements in future 3D processors. 1-6 - Yann Lamy, Jean-Philippe Colonna, G. Simon, Patrick Leduc, Séverine Cheramy, C. Laviron:
Which interconnects for which 3D applications? Status and perspectives. 1-6 - Sylvain Joblot, Alexis Farcy, Nicolas Hotellier, Amadine Jouve, François de Crecy, Arnaud Garnier, M. Argoud, C. Ferrandon, J.-P. Colonna, R. Franiatte, C. Laviron, Séverine Cheramy:
Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. 1-7 - Nyunyi M. Tshibangu, Paul D. Franzon
Design of controller for L2 cache mapped in Tezzaron stacked DRAM. 1-4 - Andy Heinig:
Layout dependent synthesis for manufacturing costs optimized 3D integrated systems. 1-6 - Jason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb:
Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination. 1-6 - Rene Puschmann, Mathias Bottcher, Irene Bartusseck, Frank Windrich
3D integration of standard integrated circuits. 1-7 - Tomasz Bieniek, Grzegorz Janczyk, Rafal Dobrowolski, Dariusz Szmigiel, Magdalena Ekwinska, Piotr Grabiec, Pawel Janus, Jerzy Zajac:
Dedicated MEMS-based test structure for 3D SiP interconnects reliability investigation. 1-6 - Satoshi Takaya, Makoto Nagata
Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. 1-4 - Hiroyuki Hashimoto, Takafumi Fukushima
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. 1-5 - S. Nishizawa, Ryohei Arima, Tomohiro Shimizu, Shoso Shingubara, Fumihiro Inoue
Highly conformal and adhesive electroless barrier and Cu seed formation using nanoparticle catalyst for realizing a high aspect ratio cu-filled TSV. 1-4 - Artur Quiring, Markus Olbrich, Erich Barke:
Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization. 1-6 - Jonghyun Cho, Youngwoo Kim, Joungho Kim, Venky Sundaram, Rao R. Tummala:
Analysis of glass interposer PDN and proposal of PDN resonance suppression methods. 1-5 - Dipanjan Gope, S. Chatterjee, D. de Araujo, Swagato Chakraborty, James Pingenot, Raul Camposano:
Device physics aware 3D electromagnetic simulation of Through-Silicon-Vias in system modeling. 1-5 - Onnik Yaglioglu, Ben Eldridge:
Contact testing of copper micro-pillars with very low damage for 3D IC assembly. 1-4 - Osamu Nukaga, Tatsuya Shioiri, Satoshi Yamamoto, Tatsuo Suemasu:
Glass interposer with high-density three-dimensional structured TGV for 3D system integration. 1-4 - William Wahby, Ashish Dembla, Muhannad S. Bakir:
Evaluation of 3DICs and fabrication of monolithic interlayer vias. 1-6 - Bei Zhang, Baohu Li, Vishwani D. Agrawal:
Yield analysis of a novel wafer manipulation method in 3D stacking. 1-8 - Frank Windrich
Front to backside alignment for TSV based 3D integration. 1-6 - Chun-Hsien Chien, Hsun Yu, Ching-Kuan Lee, Yu-Min Lin, Ren-Shin Cheng, Chau-Jie Zhan, Peng-Shu Chen, Chang-Chih Liu, Chao-Kai Hsu, Hsiang-Hung Chang, Huan-Chun Fu, Yuan-Chang Lee, Wen-Wei Shen, Cheng-Ta Ko, Wei-Chung Lo, Yung Jean Lu:
Performance and process characteristic of glass interposer with through-glass-via(TGV). 1-7 - Thorbjorn Ebefors, Jessica Fredlund, Daniel Perttu, Raymond van Dijk, Lorenzo Cifola, Mikko Kaunisto, Pekka Rantakari, Tauno Vaha-Heikkila:
The development and evaluation of RF TSV for 3D IPD applications. 1-8 - Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
TSV capacitance aware 3-D floorplanning. 1-6 - Manjari Pradhan
Optimal stacking of SOCs in a 3D-SIC for post-bond testing. 1-5 - Julia Hsin-Lin Lu, Wing-Fai Loke, Dimitrios Peroulis
Implementing wireless communication links in 3-D ICs utilizing wide-band on-chip meandering microbump antenna. 1-5 - James Quinn, Barbara Loferer:
Quality in 3D assembly - Is "Known Good Die" good enough? 1-5 - Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Using 3D-COSTAR for 2.5D test cost optimization. 1-8 - Jonghyun Cho, Youngwoo Kim, Joungho Kim, Venky Sundaram, Rao R. Tummala:
Analysis of glass interposer PDN and proposal of PDN resonance suppression methods. 1-5 - Yang Yi, Yaping Zhou:
A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D IC. 1-4 - Sayuri Kohara, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Fumiaki Yamada, Hiroyuki Mori, Yasumitsu Orii:
Thermo-mechanical evaluation of 3D packages. 1-4 - Jiye Zhang, Lin Zhang, Yuanwei Dong, Hongyu Li, Cher Ming Tan, Guangrui Xia, Chuan Seng Tan
The dependency of TSV keep-out zone (KOZ) on Si crystal direction and liner material. 1-5 - Gerald Cibrario, David Henry, Chantal Chantre, Robert Cuchet, Robert Berthelot, Karim Azizi-Mourier, Marjorie Gary, Fabien Gays:
A 3D Process Design Kit generator based on customizable 3D layout design environment. 1-5
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