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Masahiro Aoyagi
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2020 – today
- 2023
- [c25]Takeshi Ohkawa, Masahiro Aoyagi:
FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System. COOL CHIPS 2023: 1-3
2010 – 2019
- 2019
- [c24]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. 3DIC 2019: 1-3 - [c23]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi:
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC 2019: 1-4 - 2017
- [j9]Samson Melamed
, Naoya Watanabe
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 79: 380-386 (2017) - [c22]Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi:
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC 2017: 128-135 - 2016
- [j8]Wei Feng, Naoya Watanabe
Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. 59: 95-101 (2016) - [j7]Wei Feng, Tung Thanh Bui
Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. 63: 142-147 (2016) - [j6]Samson Melamed
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 67: 2-8 (2016) - [c21]Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi:
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. 3DIC 2016: 1-4 - [c20]Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura:
Wet cleaning process for high-yield via-last TSV formation. 3DIC 2016: 1-4 - [c19]Tiep Dang Dinh, Tung Thanh Bui
Two-axis tilt angle detection based on dielectric liquid capacitive sensor. IEEE SENSORS 2016: 1-3 - 2015
- [j5]Samson Melamed
Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit. Microelectron. J. 46(12): 1106-1113 (2015) - [c18]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Guard-ring monitoring system for inspecting defects in TSV-based data buses. 3DIC 2015: TS8.18.1-TS8.18.5 - [c17]Samson Melamed
Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. 3DIC 2015: TS8.30.1-TS8.30.4 - [c16]Tung Thanh Bui
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC 2015: TS8.6.1-TS8.6.4 - 2014
- [c15]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Substrate monitoring system for inspecting defects in TSV-based data buses. 3DIC 2014: 1-5 - [c14]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi:
Analysis of thermal stress distribution for TSV with novel structure. 3DIC 2014: 1-4 - [c13]Katsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama:
Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. 3DIC 2014: 1-6 - [c12]Bui Thanh Tung
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC 2014: 1-4 - [c11]Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Tsubasa Bandoh, Takahiko Mitsui, Eiichi Yamamoto:
Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal. 3DIC 2014: 1-5 - 2013
- [c10]Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi:
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC 2013: 1-5 - [c9]Katsuya Kikuchi, Fumiki Kato
Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. 3DIC 2013: 1-4 - [c8]Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai:
Special session 4C: Hot topic 3D-IC design and test. VTS 2013: 1 - 2012
- [c7]Yukoh Matsumoto, Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Fumito Imura, Hiroshi Nakagawa, Masahiro Aoyagi:
Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications. COOL Chips 2012: 1-3 - 2011
- [c6]Fumiki Kato
Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. 3DIC 2011: 1-4 - [c5]Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka:
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC 2011: 1-4 - [c4]Naoya Watanabe, Takumi Miyazaki, Masahiro Aoyagi, Kazuhiro Yoshikawa:
Damage evaluation of wet-chemical silicon-wafer thinning process. 3DIC 2011: 1-4 - [c3]Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
COOL interconnect low power interconnection technology for scalable 3D LSI design. COOL Chips 2011: 1-3
2000 – 2009
- 2009
- [c2]Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka:
Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. 3DIC 2009: 1-4 - [c1]Koichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahiro Aoyagi, Kanji Otsuka:
SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. 3DIC 2009: 1-5 - 2008
- [j4]Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi
Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect. IEICE Electron. Express 5(18): 732-737 (2008) - 2006
- [j3]Junso Pak, Masahiro Aoyagi
Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB. IEICE Trans. Electron. 89-C(4): 551-559 (2006)
1980 – 1989
- 1989
- [j2]Itaru Kurosawa, Hiroshi Nakagawa, Shin Kosaka, Masahiro Aoyagi, Susumu Takada:
A 1 kbit Josephson random access memory using variable threshold cells. IEEE J. Solid State Circuits 24(4): 1034-1040 (1989) - [j1]Hiroshi Nakagawa, Shin Kosaka, Hiroki Kawamura, Itaru Kurosawa, Masahiro Aoyagi, Youichi Hamazaki, Yoshikuni Okada, Susumu Takada:
A Josephson 4 bit RALU for a prototype computer. IEEE J. Solid State Circuits 24(4): 1076-1084 (1989)
Coauthor Index
aka: Kikuchi Katsuya
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