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Mariappan Murugesan
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2020 – today
- 2023
- [c28]Mariappan Murugesan, M. Sawa, E. Sone, Makoto Motoyoshi, Mitsumasa Koyanagi, Takafumi Fukushima
:
Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding. 3DIC 2023: 1-4 - [c27]Jiayi Shen, Chang Liu, Tadaaki Hoshi, Atsushi Sinoda, Hisashi Kino, Tetsu Tanaka, Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima
Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last. 3DIC 2023: 1-4 - 2021
- [c26]Takafumi Fukushima
Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. 3DIC 2021: 1-4 - [c25]Mariappan Murugesan, E. Sone, A. Simomura, Makoto Motoyoshi, M. Sawa, K. Fukuda, Mitsumasa Koyanagi, Takafumi Fukushima
Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications. 3DIC 2021: 1-4
2010 – 2019
- 2019
- [c24]Rui Liang, Sungho Lee, Yuki Miwa, Kousei Kumahara, Mariappan Murugesan, Hisashi Kino
Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO2 for Low-Temperature TSV Liner Formation. 3DIC 2019: 1-4 - [c23]Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima
Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI. 3DIC 2019: 1-5 - [c22]Mariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima
Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. 3DIC 2019: 1-4 - 2018
- [c21]Mariappan Murugesan, Takafumi Fukushima
Intra- and inter-chip electrical interconnection formed by directed self assembly of nanocomposite containing diblock copolymer and nanometal. IRPS 2018: 4 - 2016
- [j2]Takafumi Fukushima
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. Micromachines 7(10): 184 (2016) - [c20]Takafumi Fukushima
New concept of TSV formation methodology using Directed Self-Assembly (DSA). 3DIC 2016: 1-4 - [c19]Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi:
3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. 3DIC 2016: 1-4 - [c18]Mariappan Murugesan, Jichel Bea, Takafumi Fukushima
Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. 3DIC 2016: 1-4 - 2015
- [c17]Takafumi Fukushima
Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. 3DIC 2015: TS7.4.1-TS7.4.4 - [c16]Mariappan Murugesan, Jichoel Bea, Hiroyuki Hashimoto, K. W. Lee, Mitsu Koyanagi, Takafumi Fukushima
Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study. 3DIC 2015: TS8.10.1-TS8.10.5 - [c15]Kang Wook Lee, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. IRPS 2015: 4 - 2014
- [c14]Takafumi Fukushima
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. 3DIC 2014: 1-4 - [c13]K. W. Lee, Chisato Nagai, Ai Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima
Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. 3DIC 2014: 1-4 - [c12]Mariappan Murugesan, Takafumi Fukushima
Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI. 3DIC 2014: 1-4 - 2013
- [c11]Takafumi Fukushima
Development of via-last 3D integration technologies using a new temporary adhesive system. 3DIC 2013: 1-4 - [c10]Takafumi Fukushima
3D memory chip stacking by multi-layer self-assembly technology. 3DIC 2013: 1-4 - [c9]Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 3DIC 2013: 1-4 - [c8]Mariappan Murugesan, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. 3DIC 2013: 1-4 - 2011
- [j1]Takafumi Fukushima
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. Micromachines 2(1): 49-68 (2011) - [c7]Takafumi Fukushima
Temporary bonding strength control for self-assembly-based 3D integration. 3DIC 2011: 1-4 - [c6]Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima
W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress. 3DIC 2011: 1-4 - [c5]Mariappan Murugesan, Harufumi Kobayashi, Takafumi Fukushima
High density Cu-TSVs and reliability issues. 3DIC 2011: 1-4 - 2010
- [c4]Takafumi Fukushima
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC 2010: 1-5 - [c3]Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima
Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 3DIC 2010: 1-5
2000 – 2009
- 2009
- [c2]Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki
Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 3DIC 2009: 1-5 - [c1]Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC 2009: 1-6
Coauthor Index
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