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34th VTS 2016: Las Vegas, NV, USA
- 34th IEEE VLSI Test Symposium, VTS 2016, Las Vegas, NV, USA, April 25-27, 2016. IEEE Computer Society 2016, ISBN 978-1-4673-8454-4
- Andrzej J. Strojwas, Jacob A. Abraham, Hong Hao, Max M. Shulaker:
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below. 1-2 - Pankaj Bongale, Vinothkumar Sundaresan, Partha Ghosh, Rubin A. Parekhji:
A novel technique for interdependent trim code optimization. 1-6 - Suvadeep Banerjee
, Suriyaprakash Natarajan:
Infant mortality tests for analog and mixed-signal circuits. 1-6 - Ali Ahmadi, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris
Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs. 1-6 - Irith Pomeranz:
A convergent procedure for partially-reachable states. 1-6 - Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li
Path constraint solving based test generation for observability-enhanced branch coverage. 1-6 - Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault:
WeSPer: A flexible small delay defect quality metric. 1-6 - Sebastian Siatkowski, Chuanhe Jay Shan, Li-C. Wang
Consistency in wafer based outlier screening. 1-6 - Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, Alex Chun-Liang Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Mango C.-T. Chao:
Predicting Vt mean and variance from parallel Id measurement with model-fitting technique. 1-6 - Gregor Schatzberger, Friedrich Peter Leisenberger, Peter Sarson:
Yield improvement of an EEPROM for automotive applications while maintaining high reliability. 1-6 - Bonnie Lynne Gray:
Active polymers for bio medical microdevices and microfluidic systems. 1 - Juan Portillo, Eugene John
Building trust in 3PIP using asset-based security property verification. 1-6 - Franco Stellari, Peilin Song, Manuel Villalobos, John Sylvestri:
Revealing SRAM memory content using spontaneous photon emission. 1-6 - Jain-De Li, Sying-Jyan Wang
Test and diagnosis of paper-based microfluidic biochips. 1-6 - Kevin Greene, Vikas Chauhan
Code-modulated embedded test for phased arrays. 1-4 - Muhammad Ruhul Hasin
Post fabrication tuning of GaN based RF power amplifiers for pico-cell applications. 1-4 - Hari Chauhan, Marvin Onabajo:
Performance enhancement techniques and verification methods for radio frequency circuits and systems. 1-4 - Suriyaprakash Natarajan, Li-C. Wang:
Session 4B - Panel data analytics in semiconductor manufacturing. 1 - Juergen Alt, Paolo Bernardi
Thermal issues in test: An overview of the significant aspects and industrial practice. 1-4 - Andreas Riefert, Riccardo Cantoro
Effective generation and evaluation of diagnostic SBST programs. 1-6 - Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman:
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. 1-6 - Jianwei Zhang, Sandeep K. Gupta:
Using hardware testing approaches to improve software testing: Undetectable mutant identification. 1-6 - Yuming Zhuang
Accurate spectral testing with non-coherent sampling for large distortion to noise ratios. 1-6 - Sabyasachi Deyati, Barry John Muldrey
Adaptive testing of analog/RF circuits using hardware extracted FSM models. 1-6 - Jae Woong Jeong, Jennifer Kitchen, Sule Ozev:
Process independent gain measurement with low overhead via BIST/DUT co-design. 1-6 - Dilip Bhavsar, Michael Lohmiller, Pankaj Pant:
Lateral coupling faults in multi-ported register files and methods for their testing. 1-6 - Xuan Zuo, Sandeep K. Gupta:
Process variation oriented delay testing of SRAMs. 1-6 - Alan Becker:
Short burst software transparent on-line MBIST. 1-6 - Sandip Ray, Swarup Bhunia
Security validation in IoT space. 1 - Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty
A programmable method for low-power scan shift in SoC integrated circuits. 1-6 - Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn
Dynamic docking architecture for concurrent testing and peak power reduction. 1-6 - Surya Piplani, G. S. Visweswaran, Anshul Kumar:
Impact of crosstalk and process variation on capture power reduction for at-speed test. 1-6 - Elena-Ioana Vatajelu
Security primitives (PUF and TRNG) with STT-MRAM. 1-4 - Kaveh Shamsi, Yier Jin
Security of emerging non-volatile memories: Attacks and defenses. 1-4 - Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali
Thwarting timing attacks on NEMS relay based designs. 1-4 - Mehdi Baradaran Tahoori, Rob Aitken, Sriram R. Vangal, Bal Sandhu:
Test implications and challenges in near threshold computing special session. 1 - Yuming Zhuang
Accurate linearity testing with impure sinusoidal stimulus robust against flicker noise. 1-6 - Georgios Volanis, Dzmitry Maliuk, Yichuan Lu, Kiruba S. Subramani, Angelos Antonopoulos
On-die learning-based self-calibration of analog/RF ICs. 1-6 - Md Imran Momtaz, Suvadeep Banerjee
Real-time DC motor error detection and control compensation using linear checksums. 1-6 - Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio:
Cache- and register-aware system reliability evaluation based on data lifetime analysis. 1-6 - Sotiris Tselonis, Manolis Kaliorakis, Nikos Foutris, George Papadimitriou, Dimitris Gizopoulos:
Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level. 1-6 - Arunkumar Vijayan, Abhishek Koneru, Mojtaba Ebrahimi, Krishnendu Chakrabarty
Online soft-error vulnerability estimation for memory arrays. 1-6 - Dae Hyun Kim
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. 1-6 - Yu-Ting Li, Yong-Xiao Chen, Jin-Fu Li:
Fault modeling and testing of resistive nonvolatile-8T SRAMs. 1-6 - Jizhe Zhang, Sandeep K. Gupta:
SRAM yield-per-area optimization under spatially-correlated process variation. 1-6 - Jie Han:
Introduction to approximate computing. 1 - Fabian Oboril, Azadeh Shirvanian, Mehdi Baradaran Tahoori:
Fault tolerant approximate computing using emerging non-volatile spintronic memories. 1 - Hans-Joachim Wunderlich, Claus Braun, Alexander Schöll:
Fault tolerance of approximate compute algorithms. 1 - Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn
Flexible scan interface architecture for complex SoCs. 1-6 - Srinivasa Shashank Nuthakki
Optimization of the IEEE 1687 access network for hybrid access schedules. 1-6 - Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur:
Test method and scheme for low-power validation in modern SOC integrated circuits. 1-6 - Mike Ricchetti, Eric Rentschler, Amit Majumdar, Mike Lowe, Mark LaVine, Skip Lindsey, Sharad Kumar:
Special panel session IIB: "System validation and silicon debug - Is standardization possible?". 1 - Nikos Foutris, Athanasios Chatzidimitriou, Dimitris Gizopoulos, John Kalamatianos, Vilas Sridharan:
Faults in data prefetchers: Performance degradation and variability. 1-6 - Stavros Hadjitheophanous, Stelios N. Neophytou
Scalable parallel fault simulation for shared-memory multiprocessor systems. 1-6 - Miao Tony He, Gustavo K. Contreras, Mark M. Tehranipoor, Dat Tran, LeRoy Winemberg:
Test-point insertion efficiency analysis for LBIST applications. 1-6 - Antonio Miele
Lifetime reliability modeling and estimation in multi-core systems. 1 - Lorena Anghel, Ahmed Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard:
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results. 1 - Cristiana Bolchini:
Runtime resource management for lifetime extension in multi-core systems. 1
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