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30th ASAP 2019: New York, NY, USA
- 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019. IEEE 2019, ISBN 978-1-7281-1601-3
Applications: Machine Learning I
- Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc
, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk:
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. 1-8 - Tong Geng, Tianqi Wang, Chunshu Wu, Chen Yang, Shuaiwen Leon Song, Ang Li, Martin C. Herbordt:
LP-BNN: Ultra-low-Latency BNN Inference with Layer Parallelism. 9-16
Applications: Machine Learning II
- Zhiqiang Que
Efficient Weight Reuse for Large LSTMs. 17-24 - Jeff Anderson, Shuai Sun, Yousra Al-Kabani, Volker J. Sorger, Tarek A. El-Ghazawi:
Photonic Processor for Fully Discretized Neural Networks. 25-32
Lighting Session for Posters
- Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Thomas Chau:
Transparent Heterogeneous Cloud Acceleration. 33 - Yuancheng Li, Jiaqi Shi:
CRbS: A Code Reordering Based Speeding-up Method of Irregular Loops on CMP. 34 - Krishna Teja Chitty-Venkata, Arun K. Somani:
Impact of Structural Faults on Neural Network Performance. 35 - M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja:
Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing. 36 - Wei-pei Huang, Ray C. C. Cheung, Hong Yan:
An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation. 37 - Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku:
MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture. 38 - Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura
DeltaNet: Differential Binary Neural Network. 39 - Kamyar Givaki
Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication. 40 - Nicolas Brunie
Precision Adaptation for Fast and Accurate Polynomial Evaluation Generation. 41
Architecture and Synthesis
- H. T. Kung, Bradley McDanel, Sai Qian Zhang, Xin Dong, Chih-Chiang Chen:
Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays. 42-50 - Björn Sigurbergsson, Tom Hogervorst, Tong Dong Qiu, Razvan Nane
Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA. 51-58 - Charalampos Kritikakis, Dirk Koch:
End-to-end Dynamic Stream Processing on Maxeler HLS Platforms. 59-66 - Sharad Malik
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration. 67-70 - Dionysios Diamantopoulos, Christoph Hagleitner:
HelmGemm: Managing GPUs and FPGAs for Transprecision GEMM Workloads in Containerized Environments. 71-74
Applications: Machine Learning, Robotics, and Simulation I
- Oumaima Matoussi, Yves Durand, Olivier Sentieys, Anca Molnos:
Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: A Case Study on K-means. 75-82 - Quentin Gautier, Alric Althoff, Ryan Kastner
FPGA Architectures for Real-time Dense SLAM. 83-90 - Ce Guo, Wayne Luk, Stanley Qing Shui Loh, Alexander Warren, Joshua M. Levine:
Customisable Control Policy Learning for Robotics. 91-98 - Dawen Xu, KouZi Xing, Cheng Liu
Resilient Neural Network Training for Accelerators with Computing Errors. 99-102 - Dilshan Kumarathunga, Omega Gamage
VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing. 103-106
Hardware Acceleration
- Lixue Xia, Lansong Diao, Zhao Jiang, Hao Liang, Kai Chen, Li Ding, Shunli Dou, Zibin Su, Meng Sun, Jiansong Zhang, Wei Lin:
PAI-FCNN: FPGA Based Inference System for Complex CNN Models. 107-114
Applications: Image Processing, Networking, and Floating Point Arithmetic I
- Pankaj Bhowmik, Md Jubaer Hossain Pantho, Christophe Bobda:
Event-Based Re-configurable Hierarchical Processors for Smart Image Sensors. 115-122 - Madushan Abeysinghe, Jesse Villarreal, Lucas Weaver, Jason D. Bakos
OpenVX Graph Optimization for Visual Processor Units. 123-130 - Piyumal Ranawaka, Mongkol Ekpanyapong, Adriano Tavares
Application Specific Architecture for Hardware Accelerating HOG-SVM to Achieve High Throughput on HD Frames. 131-134
Lighting Session for Posters
- Wei-Kuo Chiang
A Quantitative Approach for Refactoring NFV-based Mobile Core Networks. 135 - Haoqiang Guo, Lu Peng, Jian Zhang, Fang Qi, Lide Duan:
Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification. 136 - Tianqi Gao, Rob A. Rutenbar
A Virtual Image Accelerator for Graph Cuts Inference on FPGA. 137 - Byeong Kil Lee, Jordan Pattee:
Implications for Hardware Acceleration of Malware Detection. 138 - Yehia Arafa, Abdel-Hameed A. Badawy, Gopinath Chennupati, Nandakishore Santhi
POSTER: GPUs Pipeline Latency Analysis. 139 - Sina Asadi, M. Hassan Najafi:
Context-Aware Number Generator for Deterministic Bit-stream Computing. 140 - Wenpei Zheng, Sheng-Yang Chiu, Jui-Chien Hsieh, Chaochang Chiu:
Smart Rabbit - A Wearable Device As An Intelligent Pacer for Marathon Runners. 141
In Memory Computing
- Shahar Kvatinsky:
Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU). 142-148 - Oscar Castañeda
PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations. 149-156 - Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Peng Huang, Jinfeng Kang:
Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design. 157-164
Applications: Machine Learning, Robotics, and Simulation II
- Rasha Karakchi, Charles Daniels, Jason D. Bakos:
An Overlay Architecture for Pattern Matching. 165-172 - Nils Voss, Peter Ziegenhein, Lukas Vermond, Joost Hoozemans, Oskar Mencer, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev
Towards Real Time Radiotherapy Simulation. 173-180 - Tianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt:
Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters. 181-184 - Sean Murray, Will Floyd-Jones, George Dimitri Konidaris, Daniel J. Sorin:
A Programmable Architecture for Robot Motion Planning Acceleration. 185-188
Emerging Technologies
- Zejun Shi, Dongqin Zhou, Keni Qiu, Jiwu Shu:
Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors. 189-196 - Saunak Saha, Henry Duwe, Joseph Zambreno:
An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators. 197-205 - Naveed Mahmud, Esam El-Araby
Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures. 206-213 - Jacqueline Lagasse, Christopher Bartoli, Wayne P. Burleson:
Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis. 214-217
Applications: Image Processing, Networking, and Floating Point Arithmetic II
- Jiuxi Meng, Nadeen Gebara, Ho-Cheung Ng, Paolo Costa, Wayne Luk:
Investigating the Feasibility of FPGA-based Network Switches. 218-226 - Brett Mathis, James E. Stine
A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. 227-234 - Nisal Ranasinghe
SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks. 235-238
Hardware Acceleration II
- Zhenman Fang, Farnoosh Javadi, Jason Cong, Glenn Reinman:
Understanding Performance Gains of Accelerator-Rich Architectures. 239-246
Design Methodologies I
- Zheming Jin, Hal Finkel:
Base64 Encoding on Heterogeneous Computing Platforms. 247-254 - Oliver Jakob Arndt, Matthias Lüders
Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics. 255-262
Design Methodologies II
- Chen Yang, Tong Geng, Tianqi Wang, Charles Lin, Jiayi Sheng, Vipin Sachdeva
Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs. 263-271 - Jian Fang
Refine and Recycle: A Method to Increase Decompression Parallelism. 272-280 - Tieu-Khanh Luong, Van-Tinh Nguyen, Anh-Thai Nguyen, Emanuel M. Popovici:
Efficient Architectures and Implementation of Arithmetic Functions Approximation Based Stochastic Computing. 281-287 - Muhammad Irfan
Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs. 288-291
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