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Joshua M. Levine
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2020 – today
- 2023
- [c14]Ce Guo, Wayne Luk, Alexander Warren, Joshua M. Levine, Peter Brookes:
Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test. ASAP 2023: 102-109 - [c13]Ce Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes:
FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization. FPL 2023: 182-188
2010 – 2019
- 2019
- [c12]Ce Guo, Wayne Luk, Stanley Qing Shui Loh, Alexander Warren, Joshua M. Levine:
Customisable Control Policy Learning for Robotics. ASAP 2019: 91-98 - 2018
- [j4]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c11]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - 2017
- [j3]Fei Xia, Ashur Rafiev, Ali Aalsaud, Mohammed A. Noaman Al-Hayanni
, James J. Davis, Joshua M. Levine, Andrey Mokhov, Alexander B. Romanovsky
Voltage, Throughput, Power, Reliability, and Multicore Scaling. Computer 50(8): 34-45 (2017) - [j2]James J. Davis
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [c10]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - 2016
- [c9]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c8]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - 2015
- [c7]Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk:
Delay-Bounded Routing for Shadow Registers. FPGA 2015: 56-65 - [c6]Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi:
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. PATMOS 2015: 103-110 - 2014
- [c5]Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre:
Timing Fault Detection in FPGA-Based Circuits. FCCM 2014: 96-99 - [c4]Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung:
Dynamic voltage & frequency scaling with online slack measurement. FPGA 2014: 65-74 - 2013
- [j1]Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong
Variation and Reliability in FPGAs. IEEE Des. Test 30(6): 50-59 (2013) - [c3]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL 2013: 1-4 - 2012
- [c2]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM 2012: 109-116 - 2011
- [c1]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA 2011: 284
Coauthor Index
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