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Hao Liang 0003
Person information
- affiliation: Hong Kong University of Science and Technology, Department of Electrical and Computer Engineering, Hong Kong
Other persons with the same name
- Hao Liang — disambiguation page
- Hao Liang 0001 — Jilin University, Department of Computer Science and Technology, Changchun, China (and 1 more)
- Hao Liang 0002
— University of Alberta, Department of Electrical and Computer Engineering, Edmonton, AB, Canada (and 1 more)
- Hao Liang 0004
- Hao Liang 0005
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2020 – today
- 2023
- [c14]Zaifeng Pan
RECom: A Compiler Approach to Accelerating Recommendation Model Inference with Massive Embedding Columns. ASPLOS (4) 2023: 268-286 - 2021
- [c13]Chunyou Su, Hao Liang, Wei Zhang, Kun Zhao, Baole Ai, Wenting Shen, Zeke Wang:
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators. FPL 2021: 211-218 - 2020
- [j6]Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. ACM Trans. Reconfigurable Technol. Syst. 13(3): 13:1-13:28 (2020) - [i1]Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang:
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. CoRR abs/2009.01441 (2020)
2010 – 2019
- 2019
- [c12]Lixue Xia, Lansong Diao, Zhao Jiang, Hao Liang, Kai Chen, Li Ding, Shunli Dou, Zibin Su, Meng Sun, Jiansong Zhang, Wei Lin:
PAI-FCNN: FPGA Based Inference System for Complex CNN Models. ASAP 2019: 107-114 - [c11]Lansong Diao, Zhao Jiang, Hao Liang, Chang'an Ye, Kai Chen, Li Ding, Shunli Dou, Meng Sun, Lixue Xia, Jiansong Zhang, Wei Lin:
PAI-FCNN: FPGA Based CNN Inference System. FPGA 2019: 184 - [c10]Jiansong Zhang, Lixue Xia, Zhao Jiang, Hao Liang, Jiaoyan Chen, Shouda Liu, Wei Lin, Yuan Xie:
Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices. Hot Chips Symposium 2019: 1-28 - 2018
- [j5]Hao Liang
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 350-363 (2018) - [j4]Zhe Lin
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. IEEE Trans. Multi Scale Comput. Syst. 4(2): 152-162 (2018) - [c9]Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha:
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. FPL 2018: 139-146 - 2017
- [j3]Liang Feng, Hao Liang, Sharad Sinha
HeteroSim: A Heterogeneous CPU-FPGA Simulator. IEEE Comput. Archit. Lett. 16(1): 38-41 (2017) - [j2]Tao Luo
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 71-75 (2017) - [c8]Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong:
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. FCCM 2017: 152-159 - 2016
- [c7]Liang Feng, Hao Liang, Sharad Sinha
HeteroSim: A heterogeneous CPU-FPGA simulator. FPL 2016: 1 - 2015
- [j1]Hao Liang
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 731-742 (2015) - [c6]Hao Liang
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. FPL 2015: 1-8 - [c5]Hao Liang, Wei Zhang
Hierarchical library based power estimator for versatile FPGAs. FPL 2015: 1 - [c4]Hao Liang
Hierarchical Library Based Power Estimator for Versatile FPGAs. MCSoC 2015: 25-32 - 2014
- [c3]Hao Liang
Hierarchical library-based power estimator for versatile FPGAs (abstract only). FPGA 2014: 243 - [c2]Rakesh Warrier, Hao Liang
Reconfigurable DSP block design for dynamically reconfigurable architecture. ISCAS 2014: 2551-2554 - 2013
- [c1]Hanhua Qian, Hao Liang
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. ASP-DAC 2013: 485-490
Coauthor Index
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