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Razvan Nane
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2020 – today
- 2023
- [i4]Tong Dong Qiu, Andreas Thune, Markus Blatt, Alf Birger Rustad, Razvan Nane:
An Evaluation and Comparison of GPU Hardware and Solver Libraries for Accelerating the OPM Flow Reservoir Simulator. CoRR abs/2309.11488 (2023) - 2022
- [j7]Nader Khammassi, Imran Ashraf, J. van Someren, Razvan Nane, Anna M. Krol, M. A. Rol
, Lingling Lao, Koen Bertels, Carmen G. Almudéver:
OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(1): 13:1-13:24 (2022) - [j6]Tom Hogervorst, Razvan Nane, Giacomo Marchiori, Tong Dong Qiu, Markus Blatt, Alf Birger Rustad:
Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 15(2): 20:1-20:35 (2022) - [i3]Razvan Nane:
SDC-based Resource Constrained Scheduling for Quantum Control Architectures. CoRR abs/2210.00794 (2022) - 2021
- [i2]Tom Hogervorst, Tong Dong Qiu, Giacomo Marchiori, Alf Birger Rustad, Markus Blatt, Razvan Nane:
Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs. CoRR abs/2101.01745 (2021) - 2020
- [j5]Jintao Yu
Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures. IEEE Trans. Emerg. Top. Comput. 8(2): 545-558 (2020) - [i1]Nader Khammassi, Imran Ashraf, J. van Someren, Razvan Nane, Anna M. Krol, M. Adriaan Rol, Lingling Lao, Koen Bertels, Carmen G. Almudéver:
OpenQL : A Portable Quantum Programming Framework for Quantum Accelerators. CoRR abs/2005.13283 (2020)
2010 – 2019
- 2019
- [c13]Björn Sigurbergsson, Tom Hogervorst, Tong Dong Qiu, Razvan Nane
Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA. ASAP 2019: 51-58 - 2017
- [j4]Hoang Anh Du Nguyen
On the Implementation of Computation-in-Memory Parallel Adder. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2206-2219 (2017) - [c12]Jintao Yu
A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons. ACM Great Lakes Symposium on VLSI 2017: 71-76 - 2016
- [j3]Razvan Nane
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1591-1604 (2016) - [c11]Adib Haron, Jintao Yu
Parallel matrix multiplication on memristor-based computation-in-memory architecture. HPCS 2016: 759-766 - [c10]Jintao Yu
Skeleton-based design and simulation flow for Computation-in-Memory architectures. NANOARCH 2016: 165-170 - [c9]Dan Iorga, Razvan Nane
An Image Processing VLIW Architecture for Real-Time Depth Detection. SBAC-PAD 2016: 158-165 - 2015
- [c8]Ghazaleh Nazarian, Razvan Nane
Low-Cost Software Control-Flow Error Recovery. DSD 2015: 510-517 - [c7]Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Razvan Nane
Computation-in-memory based parallel adder. NANOARCH 2015: 57-62 - 2014
- [b1]Razvan Nane:
Automatic Hardware Generation for Reconfigurable Architectures. Delft University of Technology, Netherlands, 2014 - [c6]Razvan Nane
High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain. EUC 2014: 138-145 - 2013
- [j2]João M. P. Cardoso
Controlling a complete hardware synthesis toolchain with LARA aspects. Microprocess. Microsystems 37(8-C): 1073-1089 (2013) - [j1]Roel Meeuws, Sayyed Arash Ostadzadeh
Quipu: A Statistical Model for Predicting Hardware Resources. ACM Trans. Reconfigurable Technol. Syst. 6(1): 3:1-3:25 (2013) - [c5]José Gabriel F. Coutinho, João M. P. Cardoso
Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract). ARC 2013: 226-228 - 2012
- [c4]Razvan Nane
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler. FPL 2012: 619-622 - [c3]Razvan Nane
Area constraint propagation in high level synthesis. FPT 2012: 247-252 - [c2]Razvan Nane
A lightweight speculative and predicative scheme for hardware execution. ReConFig 2012: 1-6 - 2011
- [c1]Razvan Nane
IP-XACT extensions for Reconfigurable Computing. ASAP 2011: 215-218
Coauthor Index
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