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Matthew M. Ziegler
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2020 – today
- 2024
- [c36]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim
, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256 - 2022
- [j12]Sae Kyu Lee
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits 57(1): 182-197 (2022) - [c35]Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch:
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning. ISPD 2022: 29-37 - 2021
- [c34]Matthew M. Ziegler, Jihye Kwon
Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper). ICCAD 2021: 1-9 - [c33]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - [c32]Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC 2021: 144-146 - 2020
- [j11]Swagath Venkataramani
Efficient AI System Design With Cross-Layer Approximate Computing. Proc. IEEE 108(12): 2232-2250 (2020) - [c31]Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j10]Andreas Burg
Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED). IEEE Des. Test 36(6): 82-83 (2019) - [j9]Matthew M. Ziegler
Research From the IEEE IBM AI Compute and Emerging Technology Symposia. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 435-438 (2019) - [c30]Jihye Kwon
A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors. DAC 2019: 218 - [c29]Nandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri
Resilient Low Voltage Accelerators for High Energy Efficiency. HPCA 2019: 147-158 - [c28]Rajiv V. Joshi, Matthew M. Ziegler:
Low Power Design From Moore to AI for nm Era : Invited Paper. MIXDES 2019: 59-64 - 2018
- [c27]Rajiv V. Joshi, Matthew M. Ziegler, Karthik Swaminathan, Nandhini Chandramoorthy:
Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications. CICC 2018: 1-4 - [c26]Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
Across the Stack Opportunities for Deep Learning Acceleration. ISLPED 2018: 35:1-35:2 - [c25]Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. VLSI Circuits 2018: 35-36 - 2017
- [j8]Matthew M. Ziegler, Ramon Bertran Monfort
Machine learning techniques for taming the complexity of modern hardware design. IBM J. Res. Dev. 61(4-5): 13:1-13:14 (2017) - [j7]Rajiv V. Joshi, Matthew M. Ziegler
A Low Voltage SRAM Using Resonant Supply Boosting. IEEE J. Solid State Circuits 52(3): 634-644 (2017) - [c24]Rajiv V. Joshi, Matthew M. Ziegler:
Programmable supply boosting techniques for near threshold and wide operating voltage SRAM. CICC 2017: 1-4 - [c23]Ramon Bertran
Very Low Voltage (VLV) Design. ICCD 2017: 601-604 - 2016
- [c22]Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni:
A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs. RES4ANT@DATE 2016: 8-12 - [c21]Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni:
A synthesis-parameter tuning system for autonomous design-space exploration. DATE 2016: 1148-1151 - [c20]Matthew M. Ziegler, Hung-Yi Liu, Luca P. Carloni
Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors. ISLPED 2016: 180-185 - [c19]Mohd Anwar, Sourav Saha, Matthew M. Ziegler, Lakshmi N. Reddy:
Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis. VLSID 2016: 116-121 - 2015
- [j6]Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny:
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59(1) (2015) - [j5]James D. Warnock, Christopher J. Berry, Michael H. Wood, Leon J. Sigal, Yun-Chan Myung, Guenter Mayer, Mark D. Mayo, Y. Chan, Frank Malgioglio, Gerald Strevig, Charudhattan Nagarajan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Howard H. Smith, Di Phan, Ricardo Nigaglioni, Thomas Strach, Matthew M. Ziegler, Niels Fricke, K. Lind, José Neves, Sridhar H. Rangarajan, J. P. Surprise, John Isakson, John Badar, Doug Malone, Donald W. Plass, A. Aipperspach, Dieter F. Wendel, Robert M. Averill III, Ruchir Puri:
IBM z13 circuit design and methodology. IBM J. Res. Dev. 59(4/5) (2015) - [j4]Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh:
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 534-543 (2015) - [c18]James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake:
4.1 22nm Next-generation IBM System z microprocessor. ISSCC 2015: 1-3 - [c17]Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan:
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. VLSIC 2015: 268- - 2014
- [c16]Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban:
POWER8 design methodology innovations for improving productivity and reducing power. CICC 2014: 1-9 - [c15]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - [c14]Ruchir Puri, Mihir R. Choudhury, Haifeng Qian
Bridging high performance and low power in processor design. ISLPED 2014: 183-188 - [c13]Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC 2014: 96-97 - 2013
- [c12]Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri:
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. ICCAD 2013: 342-348 - [c11]Matthew M. Ziegler, George Gristede, Victor V. Zyuban:
Power reduction by aggressive synthesis design space exploration. ISLPED 2013: 421-426 - [c10]Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri:
Network flow based datapath bit slicing. ISPD 2013: 139-146
2000 – 2009
- 2009
- [c9]Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich:
The opportunity cost of low power design: a case study in circuit tuning. ISLPED 2009: 133-138 - [c8]Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija:
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). PATMOS 2009: 307-316 - 2008
- [j3]Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits 43(4): 946-955 (2008) - 2007
- [c7]Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262 - [c6]Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan
Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED 2007: 275-280 - 2006
- [c5]Mircea R. Stan
Hybrid CMOS/Molecular Electronic Circuits. VLSI Design 2006: 703-708 - 2004
- [j2]Garrett S. Rose
Large-signal two-terminal device model for nanoelectronic circuit analysis. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1201-1208 (2004) - [c4]Matthew M. Ziegler, Mircea R. Stan
A Unified Design Space for Regular Parallel Prefix Adders. DATE 2004: 1386-1387 - 2003
- [j1]Mircea R. Stan
Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91(11): 1940-1957 (2003) - [c3]Matthew M. Ziegler, Mircea R. Stan
The CMOS/nano interface from a circuits perspective. ISCAS (4) 2003: 904-907 - 2002
- [c2]Matthew M. Ziegler, Mircea R. Stan
A Case for CMOS/nano co-design. ICCAD 2002: 348-352 - 2001
- [c1]Matthew M. Ziegler, Mircea Stan
Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. ISCAS (2) 2001: 657-660
Coauthor Index
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