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Monodeep Kar
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- affiliation: Georgia Institute of Technology, Atlanta, GA, USA
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2020 – today
- 2024
- [c33]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim
, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256 - 2023
- [c32]Ankur Agrawal, Monodeep Kar, Kyu-Hyoun Kim
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j13]Sae Kyu Lee
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits 57(1): 182-197 (2022) - 2021
- [j12]Nikhil Chawla
Securing IoT Devices Using Dynamic Power Management: Machine Learning Approach. IEEE Internet Things J. 8(22): 16379-16394 (2021) - [j11]Phil C. Knag
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 56(4): 1082-1092 (2021) - [c31]Chen Liu, Monodeep Kar, Xueyang Wang, Nikhil Chawla
Methodology of Assessing Information Leakage through Software-Accessible Telemetries. HOST 2021: 259-269 - [c30]He Xiao, Monodeep Kar, Saibal Mukhopadhyay, Sudhakar Yalamanchili:
VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design. ICCAE 2021: 83-88 - [c29]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - [c28]Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC 2021: 144-146 - 2020
- [j10]Arvind Singh
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO. IEEE J. Solid State Circuits 55(2): 478-493 (2020) - [j9]Raghavan Kumar
A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55(4): 945-955 (2020) - [j8]Venkata Chaitanya Krishna Chekuri
An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage. IEEE Trans. Circuits Syst. 67-II(12): 3083-3087 (2020) - [c27]Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC 2020: 392-394 - [c26]Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC 2020: 396-398 - [c25]Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits 2020: 1-2 - [c24]Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits 2020: 1-2 - [c23]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy:
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j7]Nitish Kumar
Multigated Carbon Nanotube Field Effect Transistors-Based Physically Unclonable Functions As Security Keys. IEEE Internet Things J. 6(1): 325-334 (2019) - [j6]Arvind Singh
Energy Efficient and Side-Channel Secure Cryptographic Hardware for IoT-Edge Nodes. IEEE Internet Things J. 6(1): 421-434 (2019) - [j5]Arvind Singh
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering. IEEE J. Solid State Circuits 54(2): 569-583 (2019) - [j4]Venkata Chaitanya Krishna Chekuri
Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1768-1778 (2019) - [c22]Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC 2019: 137-140 - [c21]Arvind Singh, Monodeep Kar, Nikhil Chawla
Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit. DATE 2019: 19-24 - [c20]Nikhil Chawla
Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers. HOST 2019: 31-40 - [c19]Nikhil Chawla
Application Inference using Machine Learning based Side Channel Analysis. IJCNN 2019: 1-8 - [c18]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator. ISSCC 2019: 404-406 - [c17]Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits 2019: 50- - [c16]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits 2019: 234- - [i2]Nikhil Chawla, Arvind Singh, Monodeep Kar, Saibal Mukhopadhyay:
Application Inference using Machine Learning based Side Channel Analysis. CoRR abs/1907.04428 (2019) - 2018
- [j3]Monodeep Kar
Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator. IEEE J. Solid State Circuits 53(8): 2399-2414 (2018) - [c15]Venakata Chaitanya Krishna Chekuri
Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variations. DATE 2018: 367-372 - [c14]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Exploiting on-chip power management for side-channel security. DATE 2018: 401-406 - [c13]Arvind Singh, Nikhil Chawla
Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON. HOST 2018: 159-162 - [i1]Monodeep Kar, Arvind Singh, Sanu Mathew, Santosh Ghosh, Anand Rajan, Vivek De, Raheem A. Beyah, Saibal Mukhopadhyay:
Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator. CoRR abs/1802.09096 (2018) - 2017
- [j2]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. J. Hardw. Syst. Secur. 1(4): 340-355 (2017) - [j1]Monodeep Kar
An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS. IEEE J. Solid State Circuits 52(7): 1825-1835 (2017) - [c12]Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering. ESSCIRC 2017: 51-54 - [c11]Monodeep Kar, Tushar Krishna:
A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance. ICCAD 2017: 743-750 - [c10]Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities. ISLPED 2017: 1-2 - [c9]Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. ISSCC 2017: 142-143 - 2016
- [c8]Khondker Z. Ahmed, Monodeep Kar, Saibal Mukhopadhyay:
(Invited paper) energy delivery for self-powered IoT devices. ASP-DAC 2016: 302-307 - [c7]Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS. ESSCIRC 2016: 453-456 - [c6]Arvind Singh, Monodeep Kar, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines. HOST 2016: 145-148 - [c5]Monodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
What does ultra low power requirements mean for side-channel secure cryptography? ICCD 2016: 686-689 - [c4]Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines. ISLPED 2016: 130-135 - 2015
- [c3]Arvind Singh, Monodeep Kar, Jong Hwan Ko, Saibal Mukhopadhyay:
Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators. ISLPED 2015: 134-139 - 2014
- [c2]Monodeep Kar, Denny Lie, Marilyn Wolf, Vivek De, Saibal Mukhopadhyay:
Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study. CICC 2014: 1-4 - [c1]Monodeep Kar, Sergio Carlo, Harish Kumar Krishnamurthy, Saibal Mukhopadhyay:
Impact of process variation in inductive integrated voltage regulator on delay and power of digital circuits. ISLPED 2014: 227-232
Coauthor Index
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last updated on 2024-11-30 00:16 CET by the dblp team
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