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Kevin Stawiasz
Person information
- affiliation: IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
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2010 – 2019
- 2015
- [j6]Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - [c10]Phil Oldiges, Kenneth P. Rodbell, Michael S. Gordon, John G. Massey, Kevin Stawiasz, Conal E. Murray, Henry H. K. Tang, K. Kim, K. Paul Muller:
SOI FinFET soft error upset susceptibility and analysis. IRPS 2015: 4 - [c9]Emily Ray, Barry P. Linder, Raphael Robertazzi, Kevin Stawiasz, Alan J. Weger, Emmanuel Yashchin, James H. Stathis, Peilin Song:
Analyzing path delays for accelerated testing of logic chips. IRPS 2015: 6 - 2014
- [c8]Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC 2014: 96-97 - [c7]Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. ISSCC 2014: 98-99 - 2013
- [c6]Jente B. Kuang, Keith A. Jenkins, Kevin Stawiasz, Jeremy D. Schaub:
Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators. ESSCIRC 2013: 419-422 - 2011
- [j5]Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan:
A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS. IEEE J. Solid State Circuits 46(1): 85-96 (2011) - 2010
- [c5]Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan:
A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS. ISSCC 2010: 350-351
2000 – 2009
- 2008
- [j4]Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits 43(4): 946-955 (2008) - 2007
- [j3]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou:
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs 54-II(7): 586-590 (2007) - 2004
- [c4]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz:
Experimental measurement of a novel power gating structure with intermediate power saving mode. ISLPED 2004: 20-25 - 2003
- [c3]Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, David F. Heidel, Michael Immediato:
Minimizing inductive noise in system-on-a-chip with multiple power gating structures. ESSCIRC 2003: 635-638
1990 – 1999
- 1998
- [j2]Jungwook Yang, Joongho Choi, Daniel M. Kuchta, Kevin G. Stawiasz, Petar K. Pepeljugoski, Herschel A. Ainspan:
A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology. IEEE J. Solid State Circuits 33(12): 2197-2204 (1998) - [c2]Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz:
Designing a Testable System on a Chip. VTS 1998: 2-7 - [c1]David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz:
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238 - 1995
- [j1]John R. Kirtley, Mark B. Ketchen, Chang C. Tsuei, Jonathan Z. Sun, William J. Gallagher, Lock See Yu-Jahnes, Arunava Gupta, Kevin G. Stawiasz, Shalom J. Wind:
Design and applications of a scanning SQUID microscope. IBM J. Res. Dev. 39(6): 655-668 (1995)
Coauthor Index
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