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Rahul M. Rao
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2020 – today
- 2024
- [c29]George Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao:
Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing. DATE 2024: 1-2 - 2022
- [c28]Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse:
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. ISSCC 2022: 48-50 - [c27]Naiju Karim Abdul, George Antony, Rahul M. Rao, Suriya T. Skariah:
Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning. MLCAD 2022: 83-90 - 2021
- [c26]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam
, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42
2010 – 2019
- 2019
- [j11]Shivani Bathla
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 376-386 (2019) - 2018
- [j10]Eric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort
IBM POWER9 circuit design and energy optimization for 14-nm technology. IBM J. Res. Dev. 62(4/5): 4:1-4:11 (2018) - [j9]Christopher J. Gonzalez
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53(1): 91-101 (2018) - [c25]Ankur Shukla, Rahul M. Rao, James D. Warnock:
Impact of Device Aging on Early Mode Failures in Pulsed Latches. VLSID 2018: 256-260 - [c24]Dharshak B. S., Rahul M. Rao:
A High Performance Gated Voltage Level Translator with Integrated Multiplexer. VLSID 2018: 358-361 - 2017
- [j8]Sumantra Sarkar
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3057-3066 (2017) - [c23]Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC 2017: 50-51 - 2016
- [c22]Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla:
FVCAG: A framework for formal verification driven power modeling and verification. ISLPED 2016: 260-265 - 2015
- [j7]Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny:
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59(1) (2015) - [c21]Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey:
Virtual logic netlist: Enabling efficient RTL analysis. ISQED 2015: 571-576 - 2013
- [j6]Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown:
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1683-1692 (2013) - [c20]Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. ETS 2013: 1-6 - [c19]Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez:
Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. ICCAD 2013: 458-465 - 2011
- [j5]Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang:
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 24-32 (2011) - [p1]Aditya Bansal, Rahul M. Rao:
Variations: Sources and Characterization. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 3-39 - 2010
- [j4]Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown:
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 166-170 (2010) - [c18]Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim:
Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC 2010: 1-4
2000 – 2009
- 2009
- [j3]Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim:
A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. IEEE J. Solid State Circuits 44(9): 2616-2623 (2009) - [j2]Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. 49(6): 642-649 (2009) - [c17]Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang:
A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. ISCAS 2009: 381-384 - [c16]Amlan Ghosh, Rahul M. Rao, Richard B. Brown:
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ISLPED 2009: 45-50 - 2008
- [c15]Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang:
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS 2008: 384-387 - [c14]Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown:
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED 2008: 815-820 - [c13]Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim:
A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. ISSCC 2008: 412-413 - [c12]Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown:
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design 2008: 143-149 - 2007
- [j1]Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 613-623 (2007) - 2005
- [c11]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif:
Power-aware global signaling strategies. ISCAS (1) 2005: 604-607 - [c10]Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED 2005: 88-93 - [c9]Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290 - [c8]Harmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka:
Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength. SoCC 2005: 147-150 - 2004
- [c7]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193 - [c6]Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown:
Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design 2004: 234-239 - 2003
- [c5]Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown:
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ESSCIRC 2003: 313-316 - [c4]Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown:
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD 2003: 689-692 - [c3]Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99 - [c2]Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown:
Efficient techniques for gate leakage estimation. ISLPED 2003: 100-103
1970 – 1979
- 1978
- [c1]Leland B. Jackson, Donald W. Tufts, Frank K. Soong, Rahul M. Rao:
Frequency estimation by linear prediction. ICASSP 1978: 352-356
Coauthor Index
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last updated on 2024-10-07 21:24 CEST by the dblp team
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