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IMW 2021: Dresden, Germany
- IEEE International Memory Workshop, IMW 2021, Dresden, Germany, May 16-19, 2021. IEEE 2021, ISBN 978-1-7281-8517-0
- Camille Laguna
, Mathieu Bernard, Nicolas Bernier, D. Rouchon, N. Rochat, Julien Garrione, A. Jannaud, Emmanuel Nolot, Valentina Meli, Niccolo Castellani, C. Sabbione, Guillaume Bourgeois, Marie Claire Cyrille, Liviu Militaru, A. Souifi, Gabriele Navarro
Multilayer OTS Selectors Engineering for High Temperature Stability, Scalability and High Endurance. 1-4 - Tim Kempen
50x Endurance Improvement in TaOx RRAM by Extrinsic Doping. 1-4 - Sidharth Rao
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. 1-4 - Yuta Aiba, Hitomi Tanaka, Takashi Maeda, Keiichi Sawa, Fumie Kikushima, Masayuki Miura, Toshio Fujisawa, Mie Matsuo, Hideto Horii, Hideko Mukaida, Tomoya Sanuki:
Bringing in Cryogenics to Storage: Characteristics and Performance Improvement of 3D Flash Memory. 1-4 - Jun Okuno, Takafumi Kunihiro, Kenta Konishi, Hideki Maemura, Yusuke Shuto, Fumitaka Sugaya, Monica Materano, Tarek Ali, Maximilian Lederer
High-Endurance and Low-Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application. 1-3 - K. Kaczmarek, Marie Garcia Bardon, Y. Xiang, Laurent Breuil, Nicolo Ronchi, Bertrand Parvais
Understanding the memory window in 1T-FeFET memories: a depolarization field perspective. 1-4 - Franz Schanovsky, Devin Verreck, Antonio Arreghini, Gerhard Rzepa, Zlatan Stanojevic, Christian Kernstock, Oskar Baumgartner
A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics. 1-4 - Liu Jiang, Chang Seok Kang, Ashish Pal, El Mehdi Bazizi, Tomohiko Kitajima, Nancy Fung, Gabriela Alva, Amy Child, Bhaskar Bhuyan, Takehito Koshizawa, Sung-Kwan Kang, Gill Lee, David Hwang, Blessy Alexander, Buvna Ayyagari:
Integration scheme for 3D NAND with nonreplacement word line and its cell characteristics investigation. 1-4 - Doo-Hyun Kim:
A 1 Tb 4b/cell 5th-Generation 3D-NAND Flash Memory with 2ms tPROG, 110us tR and 1.2Gb/s/pin Interface. 1-4 - Solomon Amsalu Chekol, Felix Cüppers, Rainer Waser, Susanne Hoffmann-Eifert:
An Ag/HfO2/Pt Threshold Switching Device with an Ultra-Low Leakage ( 1011), and Low Threshold Voltage (< 0.2 V) for Energy-Efficient Neuromorphic Computing. 1-4 - Jaehun Lee, Youngcheon Jeong, Kyongsik Yeom, Changmin Jeon, Jongsung Woo, Sangjin Lee, Ga-Young Lee, Dong-Hwee Hwang, Yong Seok Chung, Minji Seo, Dong-Hyun Kim, DalHwan Kim, Yongsik Kim, HyunChang Lee, Soomin Cho, MyeongHee Oh, Hyun-Jin Shin, Gun Rae Kim, Sungyoung Yoon, Yong Kyu Lee, Young Ki Hong:
Highly Reliable 28nm Embedded Flash Process Development for High-Density and High-Speed Automotive Grade-1 Application. 1-3 - Yuan-Chun Luo, Anni Lu, Jae Hur
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. 1-4 - Joel Minguet Lopez, Niccolo Castellani, Laurent Grenouillet, Lucas Reganaz, Gabriele Navarro
Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays. 1-4 - Laurent Grenouillet, Niccolo Castellani, Alain Persico, Valentina Meli, Simon Martin, Olivier Billoint, R. Segaud, Stefania Bernasconi, C. Pellissier, Carine Jahan, Christelle Charpin-Nicolle, P. Dezest, Catherine Carabasse, Paul Besombes, Sebastien Ricavy, N. P. Tran, A. Magalhaes-Lucas, A. Roman, C. Boixaderas, Thomas Magis, Messaoud Bedjaoui, M. Tessaire, A. Seignard, F. Mazen, S. Landis, Elisa Vianello, Gabriel Molas, Fred Gaillard, Julien Arcamone, Etienne Nowak
16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors. 1-4 - Matteo Baldo, Daniele Ielmini:
Modeling of oxide-based ECRAM programming by drift-diffusion ion transport. 1-4 - Steven Lequeux, Trevor Almeida, Nuno Caçoilo, Alvaro Palomino
PSA-STT-MRAM solution for extended temperature stability. 1-4 - Kenta Taoka, Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi:
Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory. 1-4 - Laura Bégon-Lours, Mattia Halter, Diana Dávila Pineda, Valeria Bragaglia, Youri Popoff, Antonio La Porta, Daniel Jubin, Jean Fompeyrine, Bert J. Offrein:
A Back-End-Of-Line Compatible, Ferroelectric Analog Non-Volatile Memory. 1-4 - Thomas Melde, Martin Trentzsch, Stefan Dünkel, Ralf Richter, Michael Otto, H. Giesler, Francois Weisbuch, N. Weddeler, Sven Beyer:
Novel embedded single poly floating gate flash demonstrated in 22nm FDSOI technology. 1-4 - Franck Melul, Thibault Kempf, Vincenzo Della Marca, Marc Bocquet, Madjid Akbal, Frederique Trenteseaux, Marc Mantelli, Arnaud Régnier, Stephan Niel, Francesco La Rosa:
Hot Electron Source Side Injection Comprehension in 40nm eSTM™. 1-4 - Koji Sakui, Nozomu Harada:
Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT). 1-4 - J. J. Sun, M. DeHerrera, B. Hughes, S. Ikegawa, H. K. Lee, Fred B. Mancoff, K. Nagel, G. Shimon, Syed M. Alam, D. Houssameddine, S. Aggarwal:
Commercialization of 1Gb Standalone Spin-Transfer Torque MRAM. 1-4 - Hitoshi Saito, Jun'ichi Watanabe, J. Seino, Tetsuro Tamura, Naoya Sashida, Kota Hara, Kuninori Kawabata, Atsushi Fujii, Jun Ohno, Atsushi Nakakubo, Manabu Kojima, T. Shimoyama, H. Wada, Lee Cleveland, H. Luan, R. Sen, N. Leong, T. Gallagher, Thomas Rueckes:
Development of 16 Mb NRAM Aiming for High Reliability, Small Cell Area, and High Switching Speed. 1-4 - Jubin Hazra, Maximilian Liehr, Karsten Beckmann
Optimization of Switching Metrics for CMOS Integrated HfO2 based RRAM Devices on 300 mm Wafer Platform. 1-4 - K. Banerjee, Laurent Breuil, A. P. Milenin, M. Pak, J. Stiers, Sean R. C. McMitchell
First demonstration of ferroelectric Si: HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application. 1-4 - Hang-Ting Lue, Tzu-Hsuan Hsu, Cheng-Lin Sung, Teng-Hao Yeh, Keh-Chung Wang, Chih-Yuan Lu:
Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. 1-4 - Wolfgang Goes, D. Green, Philippe Blaise, Giuseppe Piccolboni, Alessandro Bricalli, Amir Regev, Gabriel Molas, Jean-Francois Nodin:
A Comprehensive Oxide-Based ReRAM TCAD Model with Experimental Verification. 1-4 - Jae Hur
A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure. 1-4 - Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner
1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. 1-4 - Cheng-Lin Sung, Hang-Ting Lue, Wei-Chen Chen, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu:
First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. 1-4 - Xiaoxin Xu, Wenxuan Sun, Jie Yu, Jinru Lai, Danian Dong, Hangbing Lv:
Scaling Potential Analysis for the CMOS Compatible Ox-RRAM. 1-4 - Taras Ravsher
Threshold switching in a-Si and a-Ge based MSM selectors and its implications for device reliability. 1-4
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