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Koji Sakui
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2020 – today
- 2023
- [c8]Norio Chujo, Koji Sakui, Shinji Sugatani, Hiroyuki Ryoson, Tomoji Nakamura, Takayuki Ohba:
Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c7]Koji Sakui, Masakazu Kakumu, Nozomu Harada:
Dynamic Flash Memory with Fast Block Refresh. NVMTS 2022: 1-5 - 2021
- [c6]Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner
, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka:
1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. IMW 2021: 1-4 - [c5]Koji Sakui, Nozomu Harada:
Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT). IMW 2021: 1-4 - [c4]Zhwen Chen, Young-Suk Kim, Tadashi Fukuda, Koji Sakui, Takayuki Ohba, Tatsuji Kobayashi, Takashi Obara:
Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs. IRPS 2021: 1-6
2010 – 2019
- 2019
- [c3]Koji Sakui, Takayuki Ohba:
High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology. 3DIC 2019: 1-4 - [c2]Koji Sakui, Takayuki Ohba:
Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform. CICC 2019: 1-6 - 2010
- [j9]Tetsuo Endoh, Koji Sakui, Yukio Yasuda:
Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure. IEICE Trans. Electron. 93-C(5): 534-539 (2010) - [j8]Tetsuo Endoh, Koji Sakui, Yukio Yasuda:
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET. IEICE Trans. Electron. 93-C(5): 557-562 (2010) - [c1]Koji Sakui, Tetsuo Endoh:
A compact and low power logic design for multi-pillar vertical MOSFETs. ISCAS 2010: 309-312
2000 – 2009
- 2000
- [j7]Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, Koji Sakui:
A source-line programming scheme for low-voltage operation NAND flash memories. IEEE J. Solid State Circuits 35(5): 672-681 (2000)
1990 – 1999
- 1999
- [j6]Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa
A CMOS bandgap reference circuit with sub-1-V operation. IEEE J. Solid State Circuits 34(5): 670-674 (1999) - [j5]Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui:
A negative Vth cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories. IEEE J. Solid State Circuits 34(5): 675-684 (1999) - [j4]Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui:
A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. IEEE J. Solid State Circuits 34(11): 1536-1543 (1999) - 1997
- [j3]Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto:
A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. IEEE J. Solid State Circuits 32(5): 670-680 (1997) - 1994
- [j2]Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara:
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE J. Solid State Circuits 29(11): 1366-1373 (1994)
1980 – 1989
- 1989
- [j1]Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka:
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits 24(3): 763-770 (1989)
Coauthor Index
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