ubyhzargam / OpenSTA Public

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Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language

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Name		Name	Last commit message	Last commit date
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README.md		README.md
circuit1.v		circuit1.v

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These are the results of OpenSTA software on the above verilog codes -

Circuit1

Screenshot 2024-11-17 at 3 37 45 AM

I used the follwing SDC constraints -

Screenshot 2024-11-17 at 3 37 13 AM

I used the following TCL script -

Screenshot 2024-11-17 at 3 39 17 AM

I got the following Min and Maxz timing reports -

Screenshot 2024-11-17 at 3 40 06 AM

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Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language

electronics hdl vlsi sta opensta veilog

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