A High-performance Timing Analysis Tool for VLSI Systems

The next generation of OpenLane, rewritten from scratch with a modular architecture

ESP32 好玩、有趣、实用的项目

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

Linux generic dhcp snooping daemon using nflog and ebtables or nftables

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Static Timing Analysis Full Course

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

Free and extensible software that helps you keep track of you coding statistics

EHR DREAM Challenge

SensorThings work at DataCove

⚙️ A Sensor Things API parser

Parse tokens from an string into an array

Ceates a bidirectional link between UDP sockets and Serial port via ESP8266

State Tag Application in Vue.js

毕业设计代码【规范版本】

The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.

Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language

In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.

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