8 bit MCU design in Zedboard
-
Updated
Apr 8, 2017 - VHDL
#
veilog
Here are 2 public repositories matching this topic...
Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language
-
Updated
Nov 16, 2024 - Verilog
Improve this page
Add a description, image, and links to the veilog topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the veilog topic, visit your repo's landing page and select "manage topics."