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Tsung-Te Liu
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2020 – today
- 2024
- [j25]Tsung-Hsi Wu, Chang Shu, Tsung-Te Liu:
An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5178-5186 (2024) - [c19]Hsu-Yu Huang, Chu-Yun Hsiao, Tsung-Te Liu, James Chien-Mo Li:
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips. DAC 2024: 82:1-82:6 - [c18]Yu-Hsiang Tseng, Shao-Hong Yang, Tsung-Te Liu:
Highly Reliable PUF Circuits Using Efficient Post-Processing Stabilization Technique. ISCAS 2024: 1-5 - 2023
- [j24]Chun-Yen Yao
, Tsung-Yen Wu, Han-Chung Liang, Yu-Kai Chen, Tsung-Te Liu:
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing. IEEE J. Solid State Circuits 58(5): 1487-1495 (2023) - [j23]Bing-Chen Wu
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS. IEEE J. Solid State Circuits 58(11): 3275-3285 (2023) - [j22]Rui-Xuan Zheng, Ya-Cheng Ko
A Speculative Computation Approach for Energy-Efficient Deep Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 795-806 (2023) - [j21]Shao-Hong Yang
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 280-289 (2023) - [j20]Hua-Chien Chang, Ting Wang
A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3932-3936 (2023) - [c17]Chi-Chang Lee, Hong-Wei Chen, Chu-Song Chen, Hsin-Min Wang, Tsung-Te Liu, Yu Tsao:
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models. ASRU 2023: 1-8 - [i1]Chi-Chang Lee, Hong-Wei Chen, Chu-Song Chen, Hsin-Min Wang, Tsung-Te Liu, Yu Tsao:
LC4SV: A Denoising Framework Learning to Compensate for Unseen Speaker Verification Models. CoRR abs/2311.16604 (2023) - 2022
- [j19]Ming-Guang Lin
D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 381-392 (2022) - [j18]Jyun-Jhe Chou
CIM-Based Smart Pose Detection Sensors. Sensors 22(9): 3491 (2022) - [j17]You-Cheng Lai, Chun-Yen Yao
A Robust Area-Efficient Physically Unclonable Function With High Machine Learning Attack Resilience in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 347-355 (2022) - [j16]Shih-Hao Cheng, Meng-Hsueh Lee
A Lightweight Power Side-Channel Attack Protection Technique With Minimized Overheads Using On-Demand Current Equalizer. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4008-4012 (2022) - [j15]Yi-Long Liou, Jui-Yang Hsu
A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4178-4182 (2022) - [c16]Jung-Chun Liu
Multi-Robot Formation Control using Collective Behavior Model and Reinforcement Learning. ISCAS 2022: 2261-2265 - 2021
- [j14]Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. J. Electron. Test. 37(4): 453-471 (2021) - [c15]Bing-Chen Wu, Tsung-Te Liu:
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency. VLSI Circuits 2021: 1-2 - 2020
- [j13]Zhen-Yu Liang
A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm. IEEE J. Solid State Circuits 55(3): 817-825 (2020) - [j12]Cheng-Yao Hong
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS. IEEE J. Solid State Circuits 55(8): 2285-2294 (2020) - [j11]Ling-Yu Yeh, Po-Jen Chen, Chen-Chun Pai, Tsung-Te Liu
An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1614-1618 (2020) - [j10]Chen-Hsuan Lu, Ying-Tuan Hsu
A 270-mV 6T SRAM Using Row-Based Dual-Phase VDD Control in 28-nm CMOS. IEEE Trans. Circuits Syst. 67-I(12): 4774-4783 (2020) - [c14]Ting Wang, Tsung-Te Liu:
ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm. APCCAS 2020: 23-26 - [c13]Chia-Heng Lee, Ying-Tuan Hsu
Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications. APCCAS 2020: 193-196
2010 – 2019
- 2019
- [j9]Shang-Yuan Chang
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3504-3516 (2019) - [j8]Fu-Yan Xie
A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3631-3641 (2019) - [j7]Chia-Yuan Ku
A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1658-1662 (2019) - [c12]Bing-Chen Wu
Variation-Resilient Design Techniques for Energy-Constrained Systems. IOLTS 2019: 228-231 - 2018
- [j6]Bing-Chen Wu
Circuit Sensing Techniques in Magnetoresistive Random-Access Memory. J. Low Power Electron. 14(2): 206-216 (2018) - 2017
- [c11]Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu:
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. VLSI-DAT 2017: 1-4 - 2016
- [j5]Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu:
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1661-1672 (2016) - 2015
- [c10]Che-Min Huang, Tsung-Te Liu, Tzi-Dar Chiueh:
An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction. VLSI-DAT 2015: 1-4 - 2014
- [c9]Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava
Design Technology co-optimization for N10. CICC 2014: 1-8 - 2013
- [j4]Tsung-Te Liu, Jan M. Rabaey:
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression. IEEE J. Solid State Circuits 48(4): 897-906 (2013) - [c8]Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC 2013: 24:1-24:6 - 2012
- [c7]Tsung-Te Liu, Jan M. Rabaey:
Statistical Analysis and Optimization of Asynchronous Digital Circuits. ASYNC 2012: 1-8 - [c6]Jesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey:
Active RFID: Perpetual wireless communications platform for sensors. ESSCIRC 2012: 434-437 - [c5]Tsung-Te Liu, Jan M. Rabaey:
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression. VLSIC 2012: 158-159 - 2011
- [c4]Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey:
A low-leakage parallel CRC generator for ultra-low power applications. ISCAS 2011: 2063-2066 - [c3]Tsung-Te Liu, Jan M. Rabaey:
Linearity analysis of CMOS passive mixer. ISCAS 2011: 2833-2836 - 2010
- [j3]Dejan Markovic, Cheng C. Wang, Louis P. Alarcón, Tsung-Te Liu, Jan M. Rabaey:
Ultralow-Power Design in Near-Threshold Region. Proc. IEEE 98(2): 237-252 (2010)
2000 – 2009
- 2009
- [j2]Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey:
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic. IEEE Trans. Very Large Scale Integr. Syst. 17(7): 883-892 (2009) - 2008
- [c2]Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey:
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic. ASYNC 2008: 105-115 - 2007
- [j1]Louis P. Alarcón, Tsung-Te Liu, Matthew D. Pierson, Jan M. Rabaey:
Exploring Very Low-Energy Logic: A Case Study. J. Low Power Electron. 3(3): 223-233 (2007) - 2004
- [c1]Tsung-Te Liu, Chorng-Kuang Wang:
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator. ESSCIRC 2004: 375-378
Coauthor Index
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last updated on 2024-11-15 20:35 CET by the dblp team
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