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Aaron Thean
Aaron Voon-Yew Thean
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2020 – today
- 2023
- [j9]Hasita Veluri
, Umesh Chand, Yida Li
A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array. IEEE Trans. Neural Networks Learn. Syst. 34(8): 4416-4427 (2023) - [c40]Bangjian Zhou, Jieming Pan, Maheswari Sivan
Quantile Online Learning for Semiconductor Failure Analysis. ICASSP 2023: 1-5 - [c39]Sonu Hooda, Chun-Kuei Chen, Manohar Lal, Shih-Hao Tsai, Evgeny Zamburg, Aaron Voon-Yew Thean:
Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation. VLSI Technology and Circuits 2023: 1-2 - [i1]Bangjian Zhou, Jieming Pan, Maheswari Sivan
Quantile Online Learning for Semiconductor Failure Analysis. CoRR abs/2303.07062 (2023) - 2022
- [j8]Md Meftahul Ferdaus
Significance of activation functions in developing an online classifier for semiconductor defect detection. Knowl. Based Syst. 248: 108818 (2022) - [c38]Umesh Chand, Mohamed M. Sabry Aly, Manohar Lal, Chen Chun-Kuei, Sonu Hooda, Shih-Hao Tsai, Zihang Fang, Hasita Veluri
Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing. VLSI Technology and Circuits 2022: 326-327 - [c37]Suresh Venkatesan, James Lee, Simon Chun Kiat Goh, Brian Pile, Daniel Meerovich, Jinyu Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, Aaron Voon-Yew Thean, Yeow Kheng Lim:
A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical InterposerTM. VLSI Technology and Circuits 2022: 381-382 - 2021
- [j7]Hasita Veluri
High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks. IEEE Internet Things J. 8(11): 9219-9232 (2021) - [j6]Yuxuan Luo
A 70-μW 1.35-mm2 Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver. IEEE J. Solid State Circuits 56(7): 2065-2076 (2021) - 2020
- [j5]Yuxuan Luo
An 8.2- $\mu$ W 0.14-mm2 16-Channel CDMA-Like Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(5): 1361-1373 (2020) - [j4]Bo Xiong
A $7\times7\times2$ mm3 8.6- $\mu$ W 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications. IEEE J. Solid State Circuits 55(6): 1698-1708 (2020) - [j3]Jieming Pan
A Wireless Multi-Channel Capacitive Sensor System for Efficient Glove-Based Gesture Recognition With AI at the Edge. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1624-1628 (2020) - [c36]Abdallah M. Felfel, Kamalika Datta, Arko Dutt, Hasita Veluri
Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM. DATE 2020: 43-48 - [c35]Kamalika Datta, Arko Dutt, Ahmed Zaky, Umesh Chand, Devendra Singh, Yida Li
Fledge: Flexible Edge Platforms Enabled by In-memory Computing. DATE 2020: 1181-1186 - [c34]Jieming Pan
Seal Integrity Testing Utilizing Non-Destructive Capacitive Sensing for Product Packaging Assurance. IEEE SENSORS 2020: 1-4 - [c33]Yuxuan Luo, Yida Li
23.2 A 70µW 1.19mm2 Wireless Sensor with 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver. ISSCC 2020: 346-348
2010 – 2019
- 2019
- [c32]Bo Xiong, Yida Li
A 7×7×2mm3 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications. CICC 2019: 1-4 - [c31]Jessie Xuhua Niu, Hasita Veluri
Design of Artificial Spiking Neuron with SiO2 Memristive Synapse to Demonstrate Neuron-Level Spike Timing Dependent Plasticity. ICICDT 2019: 1-3 - 2017
- [j2]Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1669-1680 (2017) - 2016
- [c30]Tarun Agarwal, Iuliana P. Radu
Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. ESSCIRC 2016: 55-58 - [c29]Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134 - [c28]Devin Verreck, Anne S. Verhulst, Bart Soree
Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors. ESSDERC 2016: 412-415 - [c27]Nadine Collaert
Beyond-Si materials and devices for more Moore and more than Moore applications. ICICDT 2016: 1-5 - [c26]Bon Woong Ku, Peter Debacker, Dragomir Milojevic
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. ISLPED 2016: 76-81 - [c25]Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean:
5nm: Has the time for a device change come? ISQED 2016: 275-277 - 2015
- [c24]Bertrand Parvais
A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS. A-SSCC 2015: 1-4 - [c23]Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert
Holisitic device exploration for 7nm node. CICC 2015: 1-5 - [c22]Pieter Weckx, Ben Kaczer, Praveen Raghavan, Jacopo Franco, Marko Simicic
Characterization and simulation methodology for time-dependent variability in advanced technologies. CICC 2015: 1-8 - [c21]Trong Huynh Bao
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT 2015: 1-4 - [c20]Marie Garcia Bardon, P. Schuddinck, Praveen Raghavan, Doyoung Jang, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. ICICDT 2015: 1-4 - [c19]Geert Eneman, An De Keersgieter, Anda Mocuta, Nadine Collaert
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. ICICDT 2015: 1-4 - [c18]Nathalie Fievet, Praveen Raghavan, Rogier Baert, Frédéric Robert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of device and interconnect process variability on clock distribution. ICICDT 2015: 1-4 - [c17]Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean:
Modeling FinFET metal gate stack resistance for 14nm node and beyond. ICICDT 2015: 1-4 - [c16]M. Ali Pourghaderi, Anda Mocuta, Aaron Thean:
Nonparabolicity and confinement effects of IIIV materials in novel transistors. ICICDT 2015: 1-3 - [c15]Romain Ritzenthaler, Tom Schram, M. J. Cho, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Christian Caillat, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son:
I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. ICICDT 2015: 1-4 - [c14]Romain Ritzenthaler, Tom Schram, Geert Eneman, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son:
Assessment of SiGe quantum well transistors for DRAM peripheral applications. ICICDT 2015: 1-4 - [c13]Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of fin shape variability on device performance towards 10nm node. ICICDT 2015: 1-4 - [c12]Dmitry Yakimets, Doyoung Jang, Praveen Raghavan, Geert Eneman, Hans Mertens, P. Schuddinck, Arindam Mallik, Marie Garcia Bardon, Nadine Collaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Kristin De Meyer:
Lateral NWFET optimization for beyond 7nm nodes. ICICDT 2015: 1-4 - [c11]Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru
Area and routing efficiency of SWD circuits compared to advanced CMOS. ICICDT 2015: 1-4 - [c10]Jacopo Franco, Ben Kaczer, Philippe J. Roussel, Erik Bury, Hans Mertens, Romain Ritzenthaler, Tibor Grasser
NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. IRPS 2015: 2 - [c9]Ben Kaczer, Jacopo Franco, M. Cho, Tibor Grasser
Origins and implications of increased channel hot carrier variability in nFinFETs. IRPS 2015: 3 - [c8]Abhitosh Vais
The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices. IRPS 2015: 5 - [c7]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2014
- [j1]Chunmeng Dou, Dennis Lin, Abhitosh Vais, Tsvetan Ivanov, Han-Ping Chen, Koen Martens, Kuniyuki Kakushima, Hiroshi Iwai, Yuan Taur, Aaron Thean, Guido Groeseneken
Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures. Microelectron. Reliab. 54(4): 746-754 (2014) - [c6]Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava
Design Technology co-optimization for N10. CICC 2014: 1-8 - [c5]Trong Huynh Bao
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105 - [c4]Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree
System-level assessment and area evaluation of Spin Wave logic circuits. NANOARCH 2014: 25-30 - 2013
- [c3]Marc Aoulaiche, Eddy Simoen, Romain Ritzenthaler, Tom Schram, Hiroaki Arimura, Moonju Cho, Thomas Kauerauf, Guido Groeseneken
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. ESSDERC 2013: 190-193 - 2012
- [c2]Romain Ritzenthaler, Tom Schram, Erik Bury, Jérôme Mitard, L.-Å. Ragnarsson, Guido Groeseneken
Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. ESSDERC 2012: 242-245 - [c1]Tommaso Romeo, Luigi Pantisano, Eddy Simoen, Raymond Krom, Mitsuhiro Togo
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. ESSDERC 2012: 330-333
2000 – 2009
- 2001
- [b1]Aaron Thean:
Computer Modeling of Silicon Quantum Dot Floating -Gate Flash Memory Devices. University of Illinois Urbana-Champaign, USA, 2001
Coauthor Index
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