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Xiaoteng Zhao
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2020 – today
- 2024
- [j11]Zhicheng Dong
, Shubin Liu
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor. IEEE J. Solid State Circuits 59(11): 3767-3779 (2024) - [j10]Rong Zhou
A wideband low power RF Receiver Front-End for Internet-of-Things applications. Microelectron. J. 144: 106064 (2024) - [j9]Rong Zhou, Linwei Wang, Jianhang Yang
A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications. Microelectron. J. 144: 106090 (2024) - [j8]Depeng Sun, Ruiqing Wang, Feng Bu, Yuan Gao, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Rong Zhou
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators. Microelectron. J. 146: 106140 (2024) - [j7]Depeng Sun
A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and -250.8-dB FOMPLL. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1909-1913 (2024) - [c5]Zhicheng Dong, Xiaoteng Zhao, Weitan Huang, Yuan Gao, Depeng Sun, Shubin Liu, Lihong Yang, Zhangming Zhu:
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area. ISCAS 2024: 1-5 - 2023
- [j6]Lin Wang
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2637-2650 (2023) - [c4]Zhicheng Dong
A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. CICC 2023: 1-2 - 2022
- [j5]Xiaoteng Zhao
A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. IEEE J. Solid State Circuits 57(2): 546-561 (2022) - [j4]Xiaoteng Zhao
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. IEEE J. Solid State Circuits 57(5): 1358-1371 (2022) - [c3]Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. ICECS 2022 2022: 1-4 - 2021
- [j3]Xiaoteng Zhao
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 89-102 (2021) - 2020
- [c2]Xiaoteng Zhao
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. CICC 2020: 1-4
2010 – 2019
- 2019
- [j2]Xiaoteng Zhao
A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3330-3339 (2019) - [j1]Xinyi Ge
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2223-2236 (2019) - [c1]Xiaoteng Zhao
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. APCCAS 2019: 229-232
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