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"A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate ..."

Xiaoteng Zhao et al. (2019)

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DOI: 10.1109/APCCAS47518.2019.8953158

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-19

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  dblp key:
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  - https://dblp.org/rec/conf/apccas/Zhao0MM19
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. APCCAS 2019: 229-232

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