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Felice Crupi
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2020 – today
- 2024
- [j40]Fanny Spagnolo
, Stefania Perri
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1472-1484 (2024) - 2023
- [j39]Luigi Fassio
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access 11: 3584-3596 (2023) - [j38]Tatiana Moposita
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. IEEE Access 11: 144084-144094 (2023) - [j37]Tatiana Moposita
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1254-1258 (2023) - [c24]Marco Mercuri, Patrizia Vizza, Pierangelo Veltri, Felice Crupi:
OSA evaluation by using clinical parameters monitoring system based on Radar Technology. EWSN 2023: 297-298 - [i3]Massimo Vatalaro, H. Neill, F. Gity, Paolo Magnone, V. Maccaronio, C. Márquez, J. C. Galdon, F. Gamiz, Felice Crupi, P. Hurley, Raffaele De Rose:
Experimental analysis of variability in WS2-based devices for hardware security. CoRR abs/2308.02265 (2023) - 2022
- [j36]Massimo Vatalaro
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. IEEE J. Solid State Circuits 57(8): 2509-2520 (2022) - [j35]Marco Mercuri
Analysis of Signal Processing Methods to Reject the DC Offset Contribution of Static Reflectors in FMCW Radar-Based Vital Signs Monitoring. Sensors 22(24): 9697 (2022) - [j34]Stefano Laureti
Modified FMCW Scheme for Improved Ultrasonic Positioning and Ranging of Unmanned Ground Vehicles at Distances < 50 mm. Sensors 22(24): 9899 (2022) - [j33]Benjamin Zambrano
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 749-753 (2022) - [c23]Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. ICECS 2022 2022: 1-4 - [c22]Tatiana Moposita, Lionel Trojman, Felice Crupi, Marco Lanuzza
Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks. LASCAS 2022: 1-4 - [i2]Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza:
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR abs/2204.09395 (2022) - [i1]Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR abs/2205.09388 (2022) - 2021
- [j32]Luigi Fassio, Longyang Lin
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. IEEE J. Solid State Circuits 56(10): 3134-3144 (2021) - [j31]Luigi Fassio, Francesco Settino
A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1393-1397 (2021) - [j30]Luigi Fassio, Longyang Lin
A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3038-3042 (2021) - [c21]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. ESSCIRC 2021: 343-346 - [c20]Carmelo Felicetti, Marco Lanuzza
Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC. SmartIoT 2021: 229-236 - 2020
- [j29]Esteban Garzón
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. Integr. 71: 56-69 (2020) - [c19]Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c18]Marco Lanuzza
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. ASICON 2019: 1-4 - [c17]Davide Cornigli, Andrea Natale Tallarico
Characterization and Modeling of BTI in SiC MOSFETs. ESSDERC 2019: 82-85 - [c16]Esteban Garzón
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS 2019: 123-124 - [c15]Marco Lanuzza
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ICECS 2019: 158-161 - [c14]Carmelo Felicetti
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. IDCS 2019: 294-305 - [c13]Esteban Garzón
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD 2019: 85-88 - 2018
- [j28]Felice Crupi
A portable class of 3-transistor current references with low-power sub-0.5 V operation. Int. J. Circuit Theory Appl. 46(4): 779-795 (2018) - [j27]Raffaele De Rose
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 1086-1095 (2018) - [c12]Raffaele De Rose, Felice Crupi, Maksym Paliy
Design of a 3T current reference for low-voltage, low-power operation. ICICDT 2018: 13-16 - [c11]Noemi Guerra, Raffaele De Rose, Marco Guevara
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. RTSI 2018: 1-4 - 2017
- [j26]Raffaele De Rose
A physical unclonable function based on a 2-transistor subthreshold voltage divider. Int. J. Circuit Theory Appl. 45(2): 260-273 (2017) - [j25]Marco Lanuzza
Low energy/delay overhead level shifter for wide-range voltage conversion. Int. J. Circuit Theory Appl. 45(11): 1637-1646 (2017) - [j24]Marco Lanuzza
An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 61-65 (2017) - [c10]Raffaele De Rose, Domenico Albano, Felice Crupi, Marco Lanuzza
Design of a sub-1-V nanopower CMOS current reference. ECCTD 2017: 1-4 - [c9]Raffaele De Rose
A variation-aware simulation framework for hybrid CMOS/spintronic circuits. ISCAS 2017: 1-4 - [c8]Raffaele De Rose
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. SMACD 2017: 1-4 - 2015
- [j23]Luca Magnelli, Felice Crupi, Pasquale Corsonello
A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity. Int. J. Circuit Theory Appl. 43(4): 421-426 (2015) - [j22]Domenico Albano, Marco Lanuzza
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int. J. Circuit Theory Appl. 43(11): 1523-1540 (2015) - [j21]Domenico Albano, Felice Crupi, Francesca Cucchi, Giuseppe Iannaccone
A Sub-kT/q Voltage Reference Operating at 150 mV. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1547-1551 (2015) - [c7]Ben Kaczer, Jacopo Franco, M. Cho, Tibor Grasser
Origins and implications of increased channel hot carrier variability in nFinFETs. IRPS 2015: 3 - 2014
- [j20]Luca Magnelli, Francesco A. Amoroso, Felice Crupi, Gregorio Cappuccino
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier. Int. J. Circuit Theory Appl. 42(9): 967-977 (2014) - [j19]Domenico Albano, Felice Crupi, Francesca Cucchi, Giuseppe Iannaccone
A picopower temperature-compensated, subthreshold CMOS voltage reference. Int. J. Circuit Theory Appl. 42(12): 1306-1318 (2014) - [c6]Sebastiano Strangio
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. ESSDERC 2014: 282-285 - 2013
- [c5]Marc Aoulaiche, Eddy Simoen, Romain Ritzenthaler, Tom Schram, Hiroaki Arimura, Moonju Cho, Thomas Kauerauf, Guido Groeseneken
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. ESSDERC 2013: 190-193 - 2012
- [j18]Jacopo Franco
BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic. Microelectron. Reliab. 52(9-10): 1932-1935 (2012) - [j17]Raffaele De Rose
A methodology to account for the finger interruptions in solar cell performance. Microelectron. Reliab. 52(9-10): 2500-2503 (2012) - [j16]Felice Crupi, Massimo Alioto, Jacopo Franco
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements. IEEE Trans. Circuits Syst. II Express Briefs 59-II(7): 439-442 (2012) - [j15]Felice Crupi, Massimo Alioto, Jacopo Franco
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1487-1495 (2012) - [c4]Tommaso Romeo, Luigi Pantisano, Eddy Simoen, Raymond Krom, Mitsuhiro Togo
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs. ESSDERC 2012: 330-333 - [c3]Jacopo Franco
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. ICICDT 2012: 1-4 - 2011
- [j14]Luca Magnelli, Felice Crupi, Pasquale Corsonello
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. IEEE J. Solid State Circuits 46(2): 465-474 (2011) - [j13]Paolo Magnone
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1569-1582 (2011) - [c2]Felice Crupi, Massimo Alioto, Jacopo Franco
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling. ISCAS 2011: 2249-2252 - 2010
- [c1]Paolo Magnone
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits. ISCAS 2010: 1699-1702
2000 – 2009
- 2009
- [j12]Gino Giusi, Calogero Pace
Cross-correlation-based trans-impedance amplifier for current noise measurements. Int. J. Circuit Theory Appl. 37(6): 781-792 (2009) - [j11]Gino Giusi, Felice Crupi, Calogero Pace
Full Model and Characterization of Noise in Operational Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(1): 97-102 (2009) - 2008
- [j10]Calogero Pace
Detection and Classification of Single-Electron Jumps in Si Nanocrystal Memories. IEEE Trans. Instrum. Meas. 57(2): 364-368 (2008) - 2007
- [j9]Paolo Srinivasan, Felice Crupi, Eddy Simoen, Paolo Magnone
Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks. Microelectron. Reliab. 47(4-5): 501-504 (2007) - [j8]Paolo Magnone
Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics. Microelectron. Reliab. 47(12): 2109-2113 (2007) - [j7]Carmine Ciofi, Felice Crupi, Calogero Pace
A New Circuit Topology for the Realization of Very Low-Noise Wide-Bandwidth Transimpedance Amplifier. IEEE Trans. Instrum. Meas. 56(5): 1626-1631 (2007) - 2006
- [j6]Carmine Ciofi, Felice Crupi, Calogero Pace
How to enlarge the bandwidth without increasing the noise in OP-AMP-based transimpedance amplifier. IEEE Trans. Instrum. Meas. 55(3): 814-819 (2006) - [j5]Felice Crupi, Gino Giusi, Carmine Ciofi, Calogero Pace
Enhanced sensitivity cross-correlation method for voltage noise measurements. IEEE Trans. Instrum. Meas. 55(4): 1143-1147 (2006) - 2004
- [j4]A. Nannipieri, Giuseppe Iannaccone
Extraction of the trap distribution responsible for SILCs in MOS structures from the measurements and simulations of DC and noise properties. Microelectron. Reliab. 44(9-11): 1497-1501 (2004) - 2003
- [j3]Calogero Pace
Very low-noise, high-accuracy programmable voltage reference. IEEE Trans. Instrum. Meas. 52(4): 1251-1254 (2003) - [j2]Carmine Ciofi, Felice Crupi, Calogero Pace
Micro-prober for wafer-level low-noise measurements in MOS devices. IEEE Trans. Instrum. Meas. 52(5): 1533-1536 (2003) - 2002
- [j1]Carmine Ciofi, Felice Crupi, Calogero Pace
A new method for high-sensitivity noise measurements. IEEE Trans. Instrum. Meas. 51(4): 656-659 (2002)
Coauthor Index
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