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Erich Barke
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- affiliation: University of Hanover, Germany
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2010 – 2019
- 2019
- [j5]Carna Zivkovic
, Christoph Grimm
Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1785-1798 (2019) - 2018
- [c79]Bjorn Bredthauer, Markus Olbrich, Erich Barke:
STP - A Quadratic VLSI Placement Tool Using Graphic Processing Units. ISPDC 2018: 77-84 - 2016
- [c78]Erich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher:
Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysis. DATE 2016: 1102-1111 - 2015
- [c77]Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke:
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits. ASP-DAC 2015: 725-730 - [c76]Oliver Scharf, Markus Olbrich, Erich Barke:
Split and merge strategies for solving uncertain equations using affine arithmetic. SimuTools 2015: 1-8 - [c75]Artur Quiring, Markus Olbrich, Erich Barke:
Fast global interconnnect driven 3D floorplanning. VLSI-SoC 2015: 313-318 - 2014
- [c74]C. Katzschke, M.-P. Sohn, Markus Olbrich, Volker Meyer zu Bexten, Markus Tristl, Erich Barke:
Application of Mission Profiles to enable cross-domain constraint-driven design. DATE 2014: 1-6 - [c73]Michael Kärgel, Markus Olbrich, Erich Barke:
Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems. SBCCI 2014: 42:1-42:7 - 2013
- [c72]Artur Quiring, Markus Olbrich, Erich Barke:
Improving 3D-Floorplanning using smart selection operations in meta-heuristic optimization. 3DIC 2013: 1-6 - 2012
- [c71]Stefan Hoelldampf, Hyun-Sek Lukas Lee, Daniel Zaum, Markus Olbrich, Erich Barke:
Efficient generation of analog circuit models for accelerated mixed-signal simulation. SoCC 2012: 104-109 - 2011
- [c70]Artur Quiring, Marc Lindenberg, Markus Olbrich, Erich Barke:
3D floorplanning considering vertically aligned rectilinear modules using T∗-tree. 3DIC 2011: 1-5 - [c69]Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD 2011: 708-715 - [c68]Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke:
Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. ICCD 2011: 108-112 - [c67]Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
A gate sizing method for glitch power reduction. SoCC 2011: 24-29 - [c66]Min Zhang, R. Häußler, Markus Olbrich, Harald Kinzelbach, Erich Barke:
A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. VLSI Design 2011: 106-111 - 2010
- [c65]Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke:
Towards Abstract Analysis Techniques for Range Based System Simulations. FDL 2010: 159-164 - [c64]Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann:
An Accelerated Mixed-Signal Simulation Kernel for SystemC. FDL 2010: 234-239
2000 – 2009
- 2009
- [c63]Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt:
The PRAISE approach for accelerated transient analysis applied to wire models. BMAS 2009: 120-125 - [c62]Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang:
Formal approaches to analog circuit verification. DATE 2009: 724-729 - [c61]Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler:
Fast dynamic power estimation considering glitch filtering. SoCC 2009: 361-364 - 2008
- [c60]Markus Olbrich, Erich Barke:
Distribution arithmetic for stochastical analysis. ASP-DAC 2008: 537-542 - [c59]Darius Grabowski, Markus Olbrich, Erich Barke:
Analog circuit simulation using range arithmetics. ASP-DAC 2008: 762-767 - [c58]Peter Leppelt, Erich Barke:
Determining the Technical Complexity of Integrated Circuits. DATE 2008: 935 - [c57]Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke:
A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS 2008: 54-58 - [c56]Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt:
Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL 2008: 73-77 - [c55]Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22 - 2007
- [c54]Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke:
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC 2007: 706-711 - [c53]Min Zhang, Markus Olbrich, David Seider, Martin Frerichs, Harald Kinzelbach, Erich Barke:
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE 2007: 243-248 - [c52]Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke:
Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL 2007: 38-43 - [c51]Jan Torben Weinkopf, Klaus Harbich, Erich Barke:
Incremental Fault Emulation. FPL 2007: 542-545 - [c50]Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48 - [c49]Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten:
Algorithms for automatic length compensation of busses in analog integrated circuits. ISPD 2007: 159-166 - 2006
- [c48]Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke:
Using Sequential Equations to Improve Efficiency and Robustness. FDL 2006: 83-90 - [c47]Jan Torben Weinkopf, Klaus Harbich, Erich Barke:
Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. FPL 2006: 1-6 - [c46]Darius Grabowski, Christoph Grimm, Erich Barke:
Semi-symbolic modeling and simulation of circuits and systems. ISCAS 2006 - [c45]Ralf Klausen, Lars Hedrich, Erich Barke:
Vermeidung fehlerhafter Verifikations-Ergebnisse beim Äquivalenz-Vergleich nichtlinearer analoger Schaltungen. MBMV 2006: 122-131 - [c44]Darius Grabowski, Christoph Grimm, Erich Barke:
Ein Verfahren zur effizienten Analyse von Schaltungen mit Parametervarianzen. MBMV 2006: 181-190 - [c43]Daniel Platte, Shangjing Jing, Ralf Sommer, Erich Barke:
Ansätze zur Verbesserung der Simulationsperformance automatisch generierter analoger Verhaltensmodelle. MBMV 2006: 191-200 - 2005
- [c42]Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten:
Routing of analog busses with parasitic symmetry. ISPD 2005: 14-19 - [c41]Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke:
Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. FAC 2005: 37-52 - 2004
- [c40]Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke:
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE 2004: 442-447 - [c39]Markus Olbrich, Erich Barke:
Placement Using a Localization Probability Model (LPM). DATE 2004: 1412 - [c38]Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke:
Wirelength Reduction Using 3-D Physical Design. PATMOS 2004: 453-462 - 2003
- [c37]Andreas Hermann, Markus Olbrich, Erich Barke:
Placing substrate contacts into mixed-signal circuits controlling circuit performance. CICC 2003: 373-376 - [c36]Andreas Hermann, Markus Olbrich, Erich Barke:
Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18 - 2002
- [c35]Walter Hartong, Lars Hedrich, Erich Barke:
On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV 2002: 401-413 - [c34]Walter Hartong, Lars Hedrich, Erich Barke:
Model checking algorithms for analog verification. DAC 2002: 542-547 - [c33]Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke:
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE 2002: 274-278 - [c32]Walter Hartong, Lars Hedrich, Erich Barke:
An Approach to Model Checking for Nonlinear Analog Systems. DATE 2002: 1080 - [c31]Joerg Abke, Erich Barke:
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . DATE 2002: 1085 - [c30]Andreas C. Lemke, Lars Hedrich, Erich Barke:
Analog circuit sizing based on formal methods using affine arithmetic. ICCAD 2002: 486-489 - [c29]Silke Salewski, Erich Barke:
An Upper Bound for 3D Slicing Floorplans. ASP-DAC/VLSI Design 2002: 567-572 - 2001
- [c28]Joachim Küter, Erich Barke:
Architecture driven partitioning. DATE 2001: 479-487 - [c27]Markus Olbrich, Achim Rein, Erich Barke:
An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE 2001: 807 - [c26]Joerg Abke, Erich Barke:
A New Placement Method for Direct Mapping into LUT-Based FPGAs. FPL 2001: 27-36 - [c25]Klaus Harbich, Erich Barke:
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. FPL 2001: 133-141 - [c24]Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch:
CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE 2001: 71-72 - 2000
- [c23]Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke:
A current driven routing and verification methodology for analog applications. DAC 2000: 385-389 - [c22]Thorsten Adler, Erich Barke:
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE 2000: 446-450 - [c21]Matthias Ringe, Thomas Lindenkreuz, Erich Barke:
Static Timing Analysis Taking Crosstalk into Account. DATE 2000: 451-455 - [c20]Joerg Abke, Erich Barke:
CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. FPL 2000: 191-200 - [c19]Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel:
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS 2000: 306-315 - [e1]Dimitrios Soudris, Peter Pirsch, Erich Barke:
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Lecture Notes in Computer Science 1918, Springer 2000, ISBN 3-540-41068-6 [contents]
1990 – 1999
- 1999
- [c18]M. Klemme, Erich Barke:
An extended bipolar transistor model for substrate crosstalk analysis. CICC 1999: 579-582 - [c17]Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer:
A Case Study: Logic Emulation - Pitfalls and Solutions. IEEE International Workshop on Rapid System Prototyping 1999: 160- - [c16]Joerg Abke, Erich Barke, Jörn Stohmann:
A Universal Module Generator for LUT-Based FPGAs. IEEE International Workshop on Rapid System Prototyping 1999: 230-235 - 1998
- [c15]Reza Sedaghat-Maman, Erich Barke:
Real Time Fault Injection Using Logic Emulators. ASP-DAC 1998: 475-479 - [c14]Lars Hedrich, Erich Barke:
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE 1998: 649-654 - [c13]Matthias Ringe, Thomas Lindenkreuz, Erich Barke:
Path Verification Using Boolean Satisfiability. DATE 1998: 965-966 - [c12]Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke:
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL 1998: 79-88 - 1997
- [c11]Dirk Behrens, Erich Barke, Robert Tolkiehn:
Design driven partitioning. ASP-DAC 1997: 49-55 - [c10]Jörn Stohmann, Erich Barke:
A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. ICCD 1997: 489-495 - [c9]Reza Sedaghat-Maman, Erich Barke:
A new approach to fault emulation. IEEE International Workshop on Rapid System Prototyping 1997: 173-179 - 1996
- [c8]Carsten Borchers, Lars Hedrich, Erich Barke:
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC 1996: 236-239 - [c7]Frank Scherber, Erich Barke, Wolfgang Meier:
PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor. ED&TC 1996: 357-361 - [c6]Jörn Stohmann, Erich Barke:
A Universal CLA Adder Generator for SRAM-Based FPGAs. FPL 1996: 44-54 - [c5]Dirk Behrens, Klaus Harbich, Erich Barke:
Hierarchical partitioning. ICCAD 1996: 470-477 - 1995
- [c4]Lars Hedrich, Erich Barke:
A formal approach to nonlinear analog circuit verification. ICCAD 1995: 123-127
1980 – 1989
- 1988
- [j4]Erich Barke:
Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(2): 295-298 (1988) - 1985
- [j3]Erich Barke:
FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. Angew. Inform. 27(8): 328-333 (1985) - [c3]Erich Barke:
Resistance calculation from mask artwork data by finite element method. DAC 1985: 305-311 - 1984
- [j2]Erich Barke:
Figurenorientierte boolesche Maskenoperationen für die Layout-Prüfung integrierter Schaltungen / Polygon-based boolean mask operations to be used in IC design rule checking. Elektron. Rechenanlagen 26(1): 20-28 (1984) - [j1]Erich Barke:
A Network Comparison Algorithm for Layout Verification of Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(2): 135-141 (1984) - [c2]F. Luellau, T. Hoepken, Erich Barke:
A technology independent block extraction algorithm. DAC 1984: 610-615 - 1983
- [c1]Erich Barke:
A layout verification system for analog bipolar integrated circuits. DAC 1983: 353-359
Coauthor Index
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