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Journal of Electronic Testing, Volume 27
Volume 27, Number 1, February 2011
- Vishwani D. Agrawal:
Editorial. 1-2 - Muhammad Nummer, Manoj Sachdev:
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths. 9-17 - Vezio Malandruccolo, Mauro Ciappa, Hubert Rothleitner, Wolfgang Fichtner:
A New Built-In Defect-Based Testing Technique to Achieve Zero Defects in the Automotive Environment. 19-30 - Thomas Rabenalt, Michael Gössel, Andreas Leininger:
Masking of X-Values by Use of a Hierarchically Configurable Register. 31-41 - Bin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu:
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping. 43-56 - Qais Al-Gayem, Hongyuan Liu, Andrew Richardson
, Nick Burd:
Test Strategies for Electrode Degradation in Bio-Fluidic Microsystems. 57-68 - Yang Zhao, Krishnendu Chakrabarty
Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates. 69-83 - Hsin-Wen Ting, Soon-Jyh Chang, Su-Ling Huang:
A Design of Linearity Built-in Self-Test for Current-Steering DAC. 85-94
Volume 27, Number 2, April 2011
- Vishwani D. Agrawal:
Editorial. 95 - Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. 99-108 - Emil Gizdarski:
Construction and Analysis of Augmented Time Compactors. 109-122 - Desta Tadesse, R. Iris Bahar
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. 123-136 - Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs. 137-162 - Le Jin:
Application of the Kalman Filter in Linearity Testing of Analog-to-Digital Converters. 163-175 - Román Mozuelos, Yolanda Lechuga
Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor. 177-192 - Chi-Hsuan Cheng, James Chien-Mo Li:
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology. 193-201 - Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria:
Analysis of Resistive Open Defects in Drowsy SRAM Cells. 203-213 - Juan Antonio Maestro
Fault Tolerant Single Error Correction Encoders. 215-218
Volume 27, Number 3, June 2011
- Vishwani D. Agrawal:
Editorial. 219 - Haralampos-G. D. Stratigopoulos, Krishnendu Chakrabarty
Guest Editorial. 223 - Marvin Onabajo, Didac Gómez, Eduardo Aldrete-Vidrio, Josep Altet
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations. 225-240 - Sukeshwar Kannan, Bruce C. Kim, Ganesh Srinivasan, Friedrich Taenzler, Richard Antley, Craig Force:
Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither Scheme. 241-252 - Deepa Mannath, David Cohen, Victor Montaño-Martinez, Rick Hudgens, Elida de-Obaldia
Methodology to Replace Sensitivity BER and Transmit Power Production Tests in Bluetooth Devices with BiSTs. 253-266 - Gilles Fritz, Vincent Beroulle, Oum-El-Kheir Aktouf, Minh Duc Nguyen, David Hély
RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate. 267-276 - Manuel J. Barragan Asian, Rafaella Fiorelli
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures. 277-288 - Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir:
A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources. 289-303 - Manuel J. Barragan Asian, Diego Vázquez, Adoración Rueda
Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications. 305-320 - Joonsung Park, Hongjoong Shin, Jacob A. Abraham:
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model. 321-334 - Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. 335-350 - Carl Edward Gray, David C. Keezer
Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels. 351-361 - Thomas O. Myers
Assessment of Microfluidic System Testability using Fault Simulation and Test Metrics. 363-373 - Qais Al-Gayem, Andrew Richardson
An Oscillation-Based Technique for Degradation Monitoring of Sensing and Actuation Electrodes Within Microfluidic Systems. 375-387 - Lyl M. Ciganda Brasca, Paolo Bernardi
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test. 389-402 - Jeydmer Aristizabal, Badr Omrane, Clinton K. Landrock, Sasan Vosoogh-Grayli, Yindar Chuo, Jasbir N. Patel, Bozena Kaminska, Carlo Menon
Tungsten Lamps as an Affordable Light Source for Testing of Photovoltaic Cells. 403-410 - Ahmed Amine Rekik, Florence Azaïs, Norbert Dumas, Frédérick Mailly
A Behavioral Model of MEMS Convective Accelerometers for the Evaluation of Design and Calibration Strategies at System Level. 411-423
Volume 27, Number 4, August 2011
- Vishwani D. Agrawal:
Editorial. 425-426 - Test Technology Newsletter. 427-428
- Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. 429-439 - Xuan-Lun Huang, Ping-Ying Kang, Yuan-Chi Yu, Jiun-Lang Huang:
Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. 441-453 - Hsin-Wen Ting:
An Output Response Analyzer Circuit for ADC Built-in Self-Test. 455-464 - Gurusubrahmaniyan Subrahmaniyan Radhakrishnan, Sule Ozev:
Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation. 465-476 - Haijun Sun, Yongjia Zeng, Pu Li, Shaochong Lei, Zhibiao Shao:
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation. 477-484 - Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Jiang Chau Wang
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. 485-503 - Michelangelo Grosso
Functional Verification of DMA Controllers. 505-516 - Mohsen Bahramali, Jin Jiang
A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations. 517-530 - Ruthiano Simioni Munaretti, Taisy Silva Weber, Sérgio Luis Cechin, Bruno Coswig Fiss:
A Java Framework to Specify Faultloads for Fault Injection Campaigns. 531-539 - José Rodrigo Azambuja, Samuel Pagliarini
Exploring the Limitations of Software-based Techniques in SEE Fault Coverage. 541-550 - Luiz Fernando Gonçalves, Jefferson Luiz Bosa, Tiago Roberto Balen, Marcelo Lubaszewski, Eduardo Luis Schneider
Fault Detection, Diagnosis and Prediction in Electrical Valves Using Self-Organizing Maps. 551-564 - Ling Zhang, Jishun Kuang, Zhiqiang You:
Test Data Compression Using Selective Sparse Storage. 565-577
Volume 27, Number 5, October 2011
- Vishwani D. Agrawal:
Editorial. 579 - Test Technology Newsletter. 581-582
- Chia Yee Ooi, Hideo Fujiwara:
A New Design-for-Testability Method Based on Thru-Testability. 583-598 - Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. 599-609 - Jierong Guo, Yigang He, Meirong Liu:
Wavelet Neural Network Approach for Testing of Switched-Current Circuits. 611-625 - Gilles Foucard, Paul Peronnard, Raoul Velazco:
Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions. 627-633 - Marcos Barcellos Hervé, Marcelo de Souza Moraes, Pedro Almeida, Marcelo Lubaszewski, Fernanda Lima Kastensmidt
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers. 635-646 - Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect. 647-655 - Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman
Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques. 657-671 - Ashok Kavithamani, Venugopal Manikandan, Nanjundappan Devarajan:
Analog Circuit Fault Detection Using Location of Poles. 673-678 - Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan:
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect. 679
Volume 27, Number 6, December 2011
- Vishwani D. Agrawal:
Editorial. 681-682 - Test Technology Newsletter. 683-684
- Joan Font-Rosselló
Band-Pass Filter Design with Diagnosis Facilities Based on Predictive Techniques. 685-696 - Jin-Fu Lin, Hsin-Wen Ting:
Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs. 697-709 - Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan:
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. 711-721 - Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen
Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming. 723-739 - Jose Luis Garcia-Gervacio, Víctor H. Champac:
Computing the Detection Probability for Small Delay Defects of Nanometer ICs. 741-752 - Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
Symmetry Measure for Memory Test and Its Application in BIST Optimization. 753-766 - Rajat Subhra Chakraborty, Swarup Bhunia
Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation. 767-785 - Min-yong Wan, Yong Ding, Yun Pan, Xiaolang Yan:
An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture. 787-796
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