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FPT 2013: Kyoto, Japan
- 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013. IEEE 2013
Keynote Lectures
- Arif Rahman:
Recent advances in die stacking and 3D FPGA. 1 - Kazutoshi Wakabayashi:
Reconfigurable chip advantage compared with GPGPU from the compiler perspective. 2 - Paul Chow:
Why Put FPGAs in your CPU socket? 3
1.1 Best Paper Candidate Session
- Shanker Shreejith
, Suhaib A. Fahmy
Accelerating validation of time-triggered automotive systems on FPGAs. 4-11 - André DeHon, Nikil Mehta:
Exploiting partially defective LUTs: Why you don't need perfect fabrication. 12-19 - Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton:
Maximum flow algorithms for maximum observability during FPGA debug. 20-27 - Junsong Hou, Heng Yu
The architecture and placement algorithm for a uni-directional routing based 3D FPGA. 28-33
1.2 Architecture
- Charles Chiasson, Vaughn Betz:
COFFE: Fully-automated transistor sizing for FPGAs. 34-41 - S. Alexander Chin, Jason Helge Anderson:
A case for hardened multiplexers in FPGAs. 42-49 - Satoshi Jo, Amir Masoud Gharehbaghi
Debugging processors with advanced features by reprogramming LUTs on FPGA. 50-57
1.3 FPGA Applications I
- Roberto Ammendola
Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities. 58-65 - Deepak Unnikrishnan, Sandesh Gubbi Virupaksha, Lekshmi Krishnan, Lixin Gao, Russell Tessier:
Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs. 66-73 - Reetinder Sidhu:
High throughput, tree automata based XML processing using FPGAs. 74-81 - Karthikeyan Pandiyarajan, Srijith Haridas, Kuruvilla Varghese:
Transparent FPGA based device for SQL DDoS mitigation. 82-89
1.4 Power-Aware and Dynamically Reconfigurable Systems
- Tim Pifer, David M. Schwartz
Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems. 98-105 - Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima:
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor. 106-111
2.1 High Level Synthesis I
- Xitong Gao
SOAP: Structural optimization of arithmetic expressions for high-level synthesis. 112-119 - Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne:
Making domain-specific hardware synthesis tools cost-efficient. 120-127 - Kizheppatt Vipin
System-level FPGA device driver with high-level synthesis support. 128-135 - Ana Klimovic
Bitwidth-optimized hardware accelerators with software fallback. 136-143
2.2 FPGA Applications II
- Yeyong Pang, Shaojun Wang, Yu Peng, Nicholas J. Fraser, Philip Heng Wai Leong
A low latency kernel recursive least squares processor using FPGA technology. 144-151 - Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang, Lingli Wang:
Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA. 152-159 - Sebastian Kutzner, Axel Poschmann, Marc Stöttinger
TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAs. 160-167 - Zhi Ping Ang, Akash Kumar
Real-time and low power embedded ℓ1-optimization solver design. 168-175
2.3 (Special Session) Coarse Grain Reconfigurable Architectures for Graphics
- Jason Jong Kyu Park, Yongjun Park, Scott A. Mahlke:
Efficient execution of augmented reality applications on mobile programmable accelerators. 176-183 - Jeongho Nah, Jun Lee, Hongjune Kim, Jinseok Lee, Seok Joong Hwang, Donghoon Yoo, Jaejin Lee:
An OpenCL optimizing compiler for reconfigurable processors. 184-191 - Jaedon Lee, Youngsam Shin, Won-Jong Lee, Soojung Ryu, Jeongwook Kim:
Real-time ray tracing on coarse-grained reconfigurable processor. 192-197 - Kwontaek Kwon, Sungjin Son, Jeong-Soo Park, Jeongae Park, Sangoak Woo, Seokyoon Jung, Soojung Ryu:
Mobile GPU shader processor based on non-blocking Coarse Grained Reconfigurable Arrays architecture. 198-205
3.1 High Performance Computing
- Thomas C. P. Chau, Ka-Wai Kwok
Acceleration of real-time Proximity Query for dynamic active constraints. 206-213 - Xinyu Niu, José Gabriel F. Coutinho, Yu Wang, Wayne Luk:
Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters. 214-221 - Kevin Andryc, Murtaza Merchant, Russell Tessier:
FlexGrip: A soft GPGPU for FPGAs. 230-237
3.2 Physical Level EDA
- Charles Eric LaForest, J. Gregory Steffan:
Maximizing speed and density of tiled FPGA overlays via partitioning. 238-245 - Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Improving clock-rate of hard-macro designs. 246-253 - Zhenyu Guan, Justin S. J. Wong
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. 254-261 - Daniel P. Seemuth, Katherine Morrow:
Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board design. 262-269
3.3 High Level Synthesis II
- Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
From software threads to parallel hardware in high-level synthesis for FPGAs. 270-277 - Dustin Peterson, Oliver Bringmann, Thomas Schweizer, Wolfgang Rosenstiel:
StML: Bridging the gap between FPGA design and HDL circuit description. 278-285 - Tomofumi Yuki, Antoine Morvan, Steven Derrien:
Derivation of efficient FSM from loop nests. 286-293 - Vito Giovanni Castellana, Fabrizio Ferrandi
An automated flow for the High Level Synthesis of coarse grained parallel applications. 294-301
Poster Session
- Michael J. Klaiber, Donald G. Bailey
A high-throughput FPGA architecture for parallel connected components analysis based on label reuse. 302-305 - Lilian Bossuet:
Teaching FPGA security. 306-309 - Zheng Huang, Lingli Wang, Yakov Nasikovskiy, Alan Mishchenko:
Fast Boolean matching based on NPN classification. 310-313 - Anthony E. Gregerson, Aman Chadha
Multi-personality partitioning for heterogeneous systems. 314-317 - Henry Block, Tsutomu Maruyama:
A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA. 318-321 - Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Wayne Luk:
Application-specific customisation of market data feed arbitration. 322-325 - Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
A connection-based router for FPGAs. 326-329 - Sam Collinson, Oliver Sinnen
Flexible hierarchy ray tracing on FPGAs. 330-333 - Vinod Pangracious
Design and optimization of heterogeneous tree-based FPGA using 3D technology. 334-337 - Vlastimil Kosar
NFA reduction for regular expressions matching using FPGA. 338-341 - Nathan Sandoval, Casey Mackin, Sean Whitsitt
Runtime hardware/software task transition scheduling for data-adaptable embedded systems. 342-345 - Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano:
A speculative gather system for Cool Mega-Array. 346-349
Poster Session II
- Yoko Sogabe, Tsutomu Maruyama:
An acceleration method of short read mapping using FPGA. 350-353 - Jialin Chen, Lingli Wang, Bin Wang:
Quantum FPGA architecture design. 354-357 - Wenqiang Wang, Jing Yan, Ning-Yi Xu, Yu Wang, Feng-Hsiung Hsu:
Real-time high-quality stereo vision system in FPGA. 358-361 - Felix Winterstein, Samuel Bayliss, George A. Constantinides:
High-level synthesis of dynamic data structures: A case study using Vivado HLS. 362-365 - James J. Davis, Peter Y. K. Cheung:
Datapath fault tolerance for parallel accelerators. 366-369 - Ting Yu, Chris P. Bradley
Hardware acceleration of biomedical models with OpenCMISS and CellML. 370-373 - Yongzhen Chen, Miguel Rodel Felipe, Yi Wang
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. 374-377 - Qiang Liu, Zhenyu Xu, Ye Yuan:
A 66.1 Gbps single-pipeline AES on FPGA. 378-381 - Mohamad Sofian Abu Talip
Partially reconfigurable flux calculation scheme in advection term computation. 382-385 - Heinrich Riebler
FPGA-accelerated key search for cold-boot attacks against AES. 386-389 - Hongliang Su, Weihan Wang, Kuniaki Kitamori, Hideharu Amano:
A low power reconfigurable accelerator using a back-gate bias control technique. 390-393 - Moo-Kyoung Chung, Jun-Kyoung Kim, Yeon-Gon Cho, Soojung Ryu:
Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures. 394-397 - Elyas Abolhassani Ghazaani, Zana Ghaderi, Seyed Ghassem Miremadi:
A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs. 398-401
Poster Session III
- Rui Jia, Fei Wang, Rui Chen
High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients. 402-405 - Takumi Fujimori, Minoru Watanabe:
Color configuration method for an optically reconfigurable gate array. 406-409 - David Boland
Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. 410-413 - Dirk Koch, Christian Beckhoff, Alexander Wold, Jim Tørresen:
EasyPR - An easy usable open-source PR system. 414-417 - Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan, Lingli Wang:
A hardware implementation of Bag of Words and Simhash for image recognition. 418-421 - Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang, Lingli Wang:
An FPGA-cluster-accelerated match engine for content-based image retrieval. 422-425 - Hung-Lin Chao, Chun-Yang Peng, Cheng-Chien Wu, Ken-Shin Huang, Chun-Hsien Lu, Jih-Sheng Shen, Pao-Ann Hsiung:
Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design. 426-429 - Hiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi:
A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst. 430-433 - Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner
A defect-tolerant cluster in a mesh SRAM-based FPGA. 434-437 - James Arram, Wayne Luk, Peiyong Jiang:
Reconfigurable filtered acceleration of short read alignment. 438-441 - Henry Wong, Vaughn Betz, Jonathan Rose:
Efficient methods for out-of-order load/store execution for high-performance soft processors. 442-445 - Adam M. Procter, William L. Harrison, Ian Graves, Michela Becchi, Gerard Allwein:
Semantics-directed machine architecture in ReWire. 446-449 - Zhongduo Lin, Paul Chow:
ZCluster: A Zynq-based Hadoop cluster. 450-453
Demo Session
- Cory Gorman, Paul Siqueira, Russell Tessier:
An open-source SATA core for Virtex-4 FPGAs. 454-457 - Ho-Cheung Ng, Yuk-Ming Choi, Hayden Kwok-Hay So
Direct virtual memory access from FPGA for high-productivity heterogeneous computing. 458-461 - Johannes Maximilian Kühn, Thomas Schweizer, Dustin Peterson, Tommy Kuhn, Wolfgang Rosenstiel:
Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection. 462-465 - Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa
Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. 466-469 - Shanker Shreejith
Enhancing communication on automotive networks using data layer extensions. 470-473 - Takeshi Ohkawa, Takashi Yokota, Kanemitsu Ootsu:
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation. 474-477
Ph.D. Forum
- Will X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung
Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing. 478-479 - Peng Chen, Chao Wang, Xi Li, Xuehai Zhou:
Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic array. 480-481
Design Competition Papers
- Chester Liu:
Implementation of a highly scalable blokus duo solver on FPGA. 482-485 - Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
From C to Blokus Duo with LegUp high-level synthesis. 486-489 - Erik R. Altman, Joshua S. Auerbach, David F. Bacon, Ioana Baldini, Perry Cheng, Stephen J. Fink, Rodric M. Rabbah:
The Liquid Metal Blokus Duo Design. 490-493 - Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe:
FPGA Blokus Duo Solver using a massively parallel architecture. 494-497 - Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Yuki Katuta, Takushi Mitsuichi, Hideharu Amano:
Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench. 498-501 - Javier Olivito, Carlos González, Javier Resano
An FPGA-based specific processor for Blokus Duo. 502-505 - Akira Kojima:
An implementation of Blokus Duo player on FPGA. 506-509
Correction Paper
- Liang Chen, Tulika Mitra
Correction to "Graph Minor Approach for Application Mapping on CGRAs". 510
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