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Karel Bruneel
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2010 – 2019
- 2015
- [j8]Brahim Al Farisi, Karel Heyse, Karel Bruneel, João M. P. Cardoso
, Dirk Stroobandt:
Enabling FPGA routing configuration sharing in dynamic partial reconfiguration. Des. Autom. Embed. Syst. 19(1-2): 189-221 (2015) - [j7]Dionisios N. Pnevmatikatos
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocess. Microsystems 39(4-5): 321-338 (2015) - [j6]Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
TCONMAP: Technology Mapping for Parameterised FPGA Configurations. ACM Trans. Design Autom. Electr. Syst. 20(4): 48:1-48:27 (2015) - [j5]Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Identification of Dynamic Circuit Specialization Opportunities in RTL Code. ACM Trans. Reconfigurable Technol. Syst. 8(1): 4:1-4:24 (2015) - 2014
- [j4]Elias Vansteenkiste, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 370-383 (2014) - 2013
- [j3]Fatma Abouelella, Tom Davidson, Wim Meeus, Karel Bruneel, Dirk Stroobandt:
How to efficiently implement dynamic circuit specialization systems. ACM Trans. Design Autom. Electr. Syst. 18(3): 35:1-35:38 (2013) - [c25]Brahim Al Farisi, Karel Bruneel, João M. P. Cardoso
An automatic tool flow for the combined implementation of multi-mode circuits. DATE 2013: 821-826 - [c24]Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS. FPL 2013: 1-7 - [c23]Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS. FPL 2013: 1-8 - [c22]Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
A connection-based router for FPGAs. FPT 2013: 326-329 - [c21]Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
A novel tool flow for increased routing configuration similarity in multi-mode circuits. ISVLSI 2013: 96-101 - 2012
- [j2]Tom Davidson
Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment. Int. J. Reconfigurable Comput. 2012: 716984:1-716984:13 (2012) - [c20]Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration. ARC 2012: 1-12 - [c19]Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
A Connection Router for the Dynamic Reconfiguration of FPGAs. ARC 2012: 357-364 - [c18]Dionisios N. Pnevmatikatos
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. DSD 2012: 234-241 - [c17]Fatma Abouelella, Karel Bruneel, Dirk Stroobandt:
Automatically exploiting regularity in applications to reduce reconfiguration memory requirements. FPL 2012: 307-314 - [c16]Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Mapping logic to reconfigurable FPGA routing. FPL 2012: 315-321 - [c15]Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
Maximizing the reuse of routing resources in a reconfiguration-aware connection router. FPL 2012: 322-329 - 2011
- [j1]Karel Bruneel, Wim Heirman
Dynamic data folding with parameterizable FPGA configurations. ACM Trans. Design Autom. Electr. Syst. 16(4): 43:1-43:29 (2011) - [c14]Brahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs. FPL 2011: 171-176 - [c13]Tom Davidson, Mattias Merlier, Karel Bruneel, Dirk Stroobandt:
A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA. PARCO 2011: 611-618 - [c12]Robbe Vancayseele, Brahim Al Farisi, Wim Heirman
RecoNoC: A reconfigurable network-on-chip. ReCoSoC 2011: 1-2 - 2010
- [c11]Karel Bruneel, Dirk Stroobandt:
TROUTE: A Reconfigurability-Aware FPGA Router. ARC 2010: 207-218 - [c10]Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt:
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). FPGA 2010: 287 - [c9]Fatma Abouelella, Karel Bruneel, Dirk Stroobandt:
Efficiently Generating FPGA Configurations through a Stack Machine. FPL 2010: 35-39 - [c8]Tom Davidson, Karel Bruneel, Dirk Stroobandt:
Run-Time Reconfiguration for Automatic Hardware/Software Partitioning. ReConFig 2010: 424-429
2000 – 2009
- 2009
- [c7]Karel Bruneel, Fatma Abouelella, Dirk Stroobandt:
Automatically mapping applications to a self-reconfiguring platform. DATE 2009: 964-969 - [c6]Tom Davidson, Karel Bruneel, Harald Devos, Dirk Stroobandt:
Applying Parameterizable Dynamic Configurations to Sequence Alignment. PARCO 2009: 616-623 - [c5]Fatma Abouelella, Karel Bruneel, Dirk Stroobandt:
Towards a more efficient run-time FPGA configuration generation. PARCO 2009: 624-631 - 2008
- [c4]Karel Bruneel, Dirk Stroobandt:
Automatic generation of run-time parameterizable configurations. FPL 2008: 361-366 - [c3]Tom Degryse, Karel Bruneel, Harald Devos, Dirk Stroobandt:
Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. ReConFig 2008: 133-138 - [c2]Karel Bruneel, Dirk Stroobandt:
Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs. ReConFig 2008: 223-228 - 2007
- [c1]Karel Bruneel, Peter Bertels, Dirk Stroobandt:
A Method for Fast Hardware Specialization at run-time. FPL 2007: 35-40
Coauthor Index
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