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Haigang Yang
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2020 – today
- 2022
- [j18]Yong Zheng
, Haigang Yang
mTREE: A Customized Multicast-Enabled Tree-Based Network on Chip for AI Chips. IEEE Embed. Syst. Lett. 14(3): 143-146 (2022) - [j17]Yong Zheng
Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2316-2320 (2022) - 2021
- [j16]Fanyang Li, Tao Yin, Haigang Yang
A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops. Sensors 21(14): 4627 (2021) - [c39]Binghui Wang, Haigang Yang, Yiping Jia:
A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS. ISCAS 2021: 1-5 - 2020
- [j15]Tao Yin
A Phase Self-Correction Method for Bias Temperature Drift Suppression of MEMS Gyroscopes. J. Circuits Syst. Comput. 29(12): 2050198:1-2050198:17 (2020)
2010 – 2019
- 2019
- [j14]Tao Yin, Fubin Xin, Fanyang Li, Fei Liu, Haigang Yang:
A hybrid Sigma-Delta modulator with reusable SAR quantizer. IEICE Electron. Express 16(3): 20181104 (2019) - [j13]Xing Wei
A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition. Integr. 66: 164-172 (2019) - [j12]Guocheng Huang
A Sub-1 V Temperature-Insensitive-PSR Bandgap Reference with Complementary Loop Locking. J. Circuits Syst. Comput. 28(3): 1950047:1-1950047:15 (2019) - [j11]Tianwen Li
Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1276-1283 (2019) - [c38]Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao, Yiping Jia, Yong Zheng:
Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA. FPT 2019: 19-27 - [c37]Yong Zheng, Haigang Yang, Zhihong Huang, Tianli Li, Yiping Jia:
A High Energy-Efficiency FPGA-Based LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear Quantization. FPT 2019: 271-274 - [c36]Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao:
An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform. SoCC 2019: 50-55 - 2018
- [j10]Tianyi Li
A 0.5 to 1.7 Gbps PI-CDR with a Wide Frequency-Tracking Range. J. Circuits Syst. Comput. 27(4): 1850064:1-1850064:17 (2018) - [j9]Tao Yin
A 790 nW Low-Noise Instrumentation Amplifier for Bio-Sensing Based On Gm-RSC Structure. J. Circuits Syst. Comput. 27(10): 1850157:1-1850157:12 (2018) - [c35]Ning Mao, Zhihong Huang, Xing Wei, He Zhao, Xinkai Di, Le Yu, Haigang Yang:
A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only). FPGA 2018: 295 - 2017
- [c34]Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA 2017: 135-140 - 2016
- [j8]Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44(4): 92-97 (2016) - [j7]Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1297-1308 (2016) - 2015
- [j6]Wen-rui Zhu, Haigang Yang, Tongqiang Gao, Fei Liu, Tao Yin, Dandan Zhang, Hongfeng Zhang:
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 194-197 (2015) - [j5]Dandan Zhang, Hai-Gang Yang, Wen-rui Zhu, Wei Li, Zhihong Huang, Lin Li, Tianyi Li:
A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2680-2684 (2015) - [c33]Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8 - [c32]Guocheng Huang
A 1.3μW 0.7μVRMS chopper current-reuse instrumentation amplifier for EEG applications. ISCAS 2015: 2624-2627 - 2014
- [j4]Xin-Gang Wang, Hai-Gang Yang, Fei Wang, Hui He:
Successive approximation time-to-digital converter based on vernier charging method. IEICE Electron. Express 11(1): 20130885 (2014) - [c31]Tao Yin, Fubin Xin, Tongqiang Gao, Guocheng Huang
A programmable wireless platform for biomedical signal acquisition. BioCAS 2014: 296-299 - [c30]Yuanming Zhu
A -115dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique. CICC 2014: 1-4 - [c29]Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne:
Revisiting and-inverter cones. FPGA 2014: 45-54 - [c28]Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen
A survey of open source processors for FPGAs. FPL 2014: 1-6 - [c27]Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang:
Exploring architecture parameters for dual-output LUT based FPGAs. FPL 2014: 1-6 - [c26]Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin:
A semi-supervised modeling approach for performance characterization of FPGA architectures. FPL 2014: 1-6 - [c25]Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang:
Size aware placement for island style FPGAs. FPT 2014: 28-35 - [c24]Tongqiang Gao, Xiaodong Xu, Hongfeng Zhang, Haigang Yang:
A highly-integrated wireless configuration circuit for FPGA chip. ISIC 2014: 260-263 - 2013
- [j3]Xin-Gang Wang, Fei Wang, Rui Jia, Rui Chen
A Range-Extended and Area-Efficient Time-to-Digital Converter Utilizing Ring-Tapped Delay Line. IEICE Trans. Electron. 96-C(9): 1184-1194 (2013) - [j2]Huanming Wu, Haigang Yang, Tao Yin, Jiwei Jiao:
Analysis and Design of a 3rd Order Velocity-Controlled Closed-Loop for MEMS Vibratory Gyroscopes. Sensors 13(9): 12564-12580 (2013) - [c23]Dandan Zhang, Haigang Yang, Zhujia Chen, Wei Li, Zhihong Huang, Lijiang Gao, Wen-rui Zhu:
A fast-locking digital DLL with a high resolution time-to-digital converter. CICC 2013: 1-4 - [c22]Xiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang:
A CMOS Field Programmable Analog Array for intelligent sensory application. FPL 2013: 1-4 - [c21]Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang:
Timing-constrained minimum area/power FPGA memory mapping. FPL 2013: 1-4 - [c20]Rui Jia, Fei Wang, Rui Chen
High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients. FPT 2013: 402-405 - 2011
- [c19]Tao Yin, Huanming Wu, Qisong Wu, Haigang Yang, Jiwei Jiao:
A TIA-based interface for MEMS capacitive gyroscope. ASICON 2011: 149-152 - [c18]Xiaoyu Wang, Haigang Yang, Tao Yin, Fei Liu:
A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter design. ASICON 2011: 445-448 - [c17]Huanming Wu, Haigang Yang, Xiaoyan Cheng, Tao Yin, Jiwei Jiao:
Integrated Gm-C based PI controller for MEMS gyroscope drive loop. ASICON 2011: 858-861 - [c16]Fanyang Li, Haigang Yang, Yu Wang, Qisong Wu:
Current Mode Feed-Forward Gain Control for 0.8V CMOS hearing aid. ISCAS 2011: 793-796 - [c15]Wen-rui Zhu, Haigang Yang, Tongqiang Gao:
A novel low voltage Subtracting BandGap Reference with temperature coefficient of 2.2 ppm/°. ISCAS 2011: 2281-2284 - [c14]Tao Yin, Huanming Wu, Qisong Wu, Haigang Yang, Jiwei Jiao:
A TIA-based readout circuit with temperature compensation for MEMS capacitive gyroscope. NEMS 2011: 401-405 - [c13]Le Yu, Haigang Yang, Jia Zhang, Wei Wang:
Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC. VLSI-SoC 2011: 94-97 - [c12]Jia Zhang, Le Yu, Haigang Yang, Y. L. Xie, F. B. Zhou, Wei Wang:
Self-test method and recovery mechanism for high frequency TSV array. VLSI-SoC 2011: 260-265 - 2010
- [c11]Xin Cheng, Haigang Yang, Tongqiang Gao, Fei Liu:
A 47-dB linear CMOS variable gain amplifier using current squaring technique. APCCAS 2010: 76-79 - [c10]Hui Zhang, Haigang Yang, Fei Liu, Yuan-feng Wei, Jia Zhang:
Start-up analysis for differential ring oscillator with even number of stages. APCCAS 2010: 636-639 - [c9]Le Yu, Haigang Yang, Tom T. Jing, Min Xu, Robert E. Geer, Wei Wang:
Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs. ICCAD 2010: 686-693 - [c8]Hai-Gang Yang:
Overview: Emerging technologies on giga-scale FPGA implementat. ISCAS 2010: 1428-1431 - [c7]Chong Zhang, Qisong Wu, Tao Yin, Haigang Yang:
A MEMS gyroscope readout circuit with temperature compensation. NEMS 2010: 458-462
2000 – 2009
- 2009
- [c6]Ming Liu, Haigang Yang, Sansiri Tanachutiwat, Wei Wang:
FPGA based on integration of carbon nanorelays and CMOS devices. NANOARCH 2009: 61-64 - [c5]Ming Liu, Haigang Yang, Sansiri Tanachutiwat, Wei Wang:
Carbon Nanotube Nanorelays with Pass-Transistor for FPGA Routing Devices. NanoNet 2009: 57-63 - 2008
- [c4]Quan Yuan, Haigang Yang, Fang-yuan Dong, Tao Yin:
"Time borrowing" technique for design of low-power high-speed multi-modulus prescaler in frequency synthesizer. ISCAS 2008: 1004-1007 - 2006
- [c3]Tao Yin, Haigang Yang, Quan Yuan, Guoping Cui:
Noise Analysis and Simulation of Chopper Amplifier. APCCAS 2006: 167-170 - 2005
- [c2]Zengjin Lin, Haigang Yang, Lungui Zhong, Jiabin Sun, Shanhong Xia:
Impact of capacitor array mismatch in embedded CMOS CR SAR ADC design. Circuits, Signals, and Systems 2005: 165-168 - [c1]Haigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong:
A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology. IWSOC 2005: 180-183
1990 – 1999
- 1994
- [j1]Hai-Gang Yang, Steve Fluxman, Carlo Reita, Piero Migliorato:
Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers. IEEE J. Solid State Circuits 29(6): 727-732 (1994)
Coauthor Index
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last updated on 2024-08-15 23:46 CEST by the dblp team
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