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Sumanta Chaudhuri
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2020 – today
- 2024
- [c27]Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione:
Find the Lady: Permutation and Re-synchronization of Deep Neural Networks. AAAI 2024: 21001-21009 - [c26]Carl De Sousa Trias, Mihai Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione:
WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking. ICPR (5) 2024: 301-317 - [c25]Quentin Forcioli, Sumanta Chaudhuri, Jean-Luc Danger:
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments. ISQED 2024: 1-8 - [i8]Carl De Sousa Trias, Mihai Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione:
WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking. CoRR abs/2409.03902 (2024) - 2023
- [c24]Carl De Sousa Trias, Mihai Mitrea, Enzo Tartaglione, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri:
A Hitchhiker's Guide to White-Box Neural Network Watermarking Robustness. EUVIP 2023: 1-6 - [c23]Quentin Forcioli, Jean-Luc Danger, Sumanta Chaudhuri:
A gem5 based Platform for Micro-Architectural Security Analysis. HASP@MICRO 2023: 91-99 - [i7]Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione:
Find the Lady: Permutation and Re-Synchronization of Deep Neural Networks. CoRR abs/2312.14182 (2023) - 2022
- [c22]Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner:
Minconvnets: a New Class of Multiplication-Less Neural Networks. ICIP 2022: 881-885 - 2021
- [i6]Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner:
MinConvNets: A new class of multiplication-less Neural Networks. CoRR abs/2101.09492 (2021) - 2020
- [c21]Xuecan Yang, Sumanta Chaudhuri, Lirida A. B. Naviner, Laurence Likforman:
Quad-Approx CNNs for Embedded Object Detection Systems. ICECS 2020: 1-4
2010 – 2019
- 2018
- [c20]Sumanta Chaudhuri:
A security vulnerability analysis of SoCFPGA architectures. DAC 2018: 139:1-139:6 - [c19]Sumanta Chaudhuri:
Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices. ISMVL 2018: 38-43 - 2017
- [c18]Sumanta Chaudhuri:
Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). FPGA 2017: 295-296 - 2016
- [i5]Sumanta Chaudhuri, Tarik Graba, Yves Mathieu:
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR abs/1609.08681 (2016) - 2014
- [j3]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express 11(3): 20130912 (2014) - [j2]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express 11(3): 20140011 (2014) - 2013
- [c17]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
A variation-adaptive retiming method exploiting reconfigurability. FPL 2013: 1-4 - [c16]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT 2013: 254-261 - 2012
- [c15]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522 - [i4]Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
Cross-point architecture for spin transfer torque magnetic random access memory. CoRR abs/1202.1782 (2012) - 2011
- [c14]Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung:
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT 2011: 1-8 - [i3]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011) - [i2]Sumanta Chaudhuri, Sylvain Guilley:
Side-Channel Oscilloscope. CoRR abs/1103.1824 (2011) - 2010
- [c13]Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
High Density Asynchronous LUT Based on Non-volatile MRAM Technology. FPL 2010: 374-379 - [c12]Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
Design of embedded MRAM macros for memory-in-logic applications. ACM Great Lakes Symposium on VLSI 2010: 155-158
2000 – 2009
- 2009
- [c11]Sumanta Chaudhuri:
Diagonal tracks in FPGAs: a performance evaluation. FPGA 2009: 245-248 - [c10]Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet:
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS 2009: 351-354 - 2008
- [j1]Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri:
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57(11): 1482-1497 (2008) - [c9]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 - [c8]Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger:
An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125 - [c7]Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley:
Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257 - [c6]Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong:
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32 - [c5]Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger:
Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18 - [i1]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks. CoRR abs/0809.3942 (2008) - 2007
- [c4]Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley:
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL 2007: 665-669 - [c3]Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst:
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372 - [c2]Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22 - 2006
- [c1]Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst:
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig 2006: 47-55
Coauthor Index
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