default search action
ETS 2015: Cluj-Napoca, Romania
- 20th IEEE European Test Symposium, ETS 2015, Cluj-Napoca, Romania, 25-29 May, 2015. IEEE 2015, ISBN 978-1-4799-7603-4
- Douglas Goodman:
Expanding the boundaries of test and diagnostics: Prognostics and Health Management (PHM) for complex systems. 1 - Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue:
A practical approach for logic simplification based on fault acceptability for error tolerant application. 1-2 - Flavius Opritoiu, Mircea Vladutiu:
Evaluating the self-testing property of AES' finite field inversion units. 1-2 - Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
, Krishnendu Chakrabarty
Testing of digital microfluidic biochips with arbitrary layouts. 1-2 - Paolo Bernardi
Software-based self-test techniques of computational modules in dual issue embedded processors. 1-2 - Shuo Li, Hong Wang, Shiyuan Yang:
Reliability analysis for power MOSFET based on multi-physics simulation. 1-2 - Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre:
Session-less based thermal-aware 3D-SIC test scheduling. 1-2 - Imran Wali, Arnaud Virazel
An effective hybrid fault-tolerant architecture for pipelined cores. 1-6 - Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato:
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. 1-6 - Abbas BanaiyanMofrad, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori, Nikil D. Dutt
Protecting caches against multi-bit errors using embedded erasure coding. 1-6 - Ismail Emre Araci, Paul Pop
Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design. 1-8 - Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao:
Branch guided functional test generation at the RTL. 1-6 - Karsten Scheibler, Dominik Erb, Bernd Becker
Improving test pattern generation in presence of unknown values beyond restricted symbolic logic. 1-6 - Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Reliability-aware operation chaining in high level synthesis. 1-6 - Atsushi Hirai, Yukari Yamauchi, Toshinori Hosokawa, Masayuki Arai:
A low capture power test generation method using capture safe test vectors. 1-2 - Stelios N. Neophytou
Tackling the complexity of exact path delay fault grading for path intensive circuits. 1-2 - Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue:
Designing area-efficient controllers for multi-cycle transient fault tolerant systems. 1-2 - Infall Syafalni
A soft-error tolerant TCAM using partial don't-care keys. 1-2 - Ioannis Voyiatzis:
Symmetric transparent on-line BIST of word-organized memories with binary adders. 1-2 - Alessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo:
A Bayesian model for system level reliability estimation. 1-2 - Fotios Vartziotis
A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs. 1-2 - Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui:
On resistive open defect detection in DRAMs: The charge accumulation effect. 1-6 - Elena I. Vatajelu
Power-aware voltage tuning for STT-MRAM reliability. 1-6 - Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases. 1-6 - Hans-Joachim Wunderlich:
Testing visions. 1 - Jinbo Wan, Hans G. Kerkhoff:
New drain current model for nano-meter MOS transistors on-chip threshold voltage test. 1-6 - Daniele Rossi
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating. 1-6 - Nils Heidmann, Nico Hellwege, Steffen Paul
Variability-aware aging modeling for reliability analysis of an analog neural measurement system. 1-6 - Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
Automatic generation of autonomous built-in observability structures for analog circuits. 1-6 - Gildas Léger
Boundary cost optimization for Alternate Test. 1-6 - David C. Keezer
An FPGA-based ATE extension module for low-cost multi-GHz memory test. 1-6 - Zebo Peng:
Is adaptive testing the panacea for the future test problems? 1 - Yu Huang, Wu Yang, Wu-Tung Cheng:
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies. 1-10 - Bram Kruseman:
Testing of Analog/Mixed Signal ICs: Past, present and future. 1 - Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu:
High frequency jitter estimator for SoCs. 1-6 - Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre:
A new technique for low-cost phase noise production testing from 1-bit signal acquisition. 1-6 - Jae Woong Jeong, Jennifer Kitchen, Sule Ozev:
Robust amplitude measurement for RF BIST applications. 1-6 - Charalambos Konstantinou
Cyber-physical systems: A security perspective. 1-8 - Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue:
A fault tolerant response analyzer with self-error-correction capability. 1-2 - Yukiya Miura, Tatsunori Ikeda:
LSI aging estimation using ring oscillators. 1-2 - Mario Schölzel, Patryk Skoncej:
Software-based repair for memories in tiny embedded systems. 1-2 - Jihun Jung, Muhammad Adil Ansari, Dooyoung Kim, Hyunbean Yi, Sungju Park:
Efficient diagnosis technique for aging defects on automotive semiconductor chips. 1-2 - Farshad Firouzi, Fangming Ye, Arunkumar Vijayan, Abhishek Koneru, Krishnendu Chakrabarty
Re-using BIST for circuit aging monitoring. 1-2 - Stephan Eggersglüß:
Compact test set generation for test compression-based designs. 1-6 - Jishun Kuang, Liang Zhang, Zhiqiang You, Yingbo Zhou:
Improve the compression ratios for code-based test vector compressions by decomposing. 1-6 - Marco Gaudesi, Matteo Sonza Reorda
On test program compaction. 1-6 - Florence Azaïs:
Analog test: Why still "à la mode" after more than 25 years of research? 1 - Kohei Miyase, Matthias Sauer, Bernd Becker
Identification of high power consuming areas with gate type and logic level information. 1-6 - Vasileios Tenentes
Diagnosis of power switches with power-distribution-network consideration. 1-6 - Mohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Aging guardband reduction through selective flip-flop optimization. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-26 00:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: