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Michael A. Sperling
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2020 – today
- 2020
- [j5]Miguel E. Perez
, Michael A. Sperling, John F. Bulzacchelli
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS. IEEE J. Solid State Circuits 55(3): 731-743 (2020)
2010 – 2019
- 2019
- [c7]Miguel E. Perez, Michael A. Sperling, Timothy E. Diemoz, John F. Bulzacchelli, Zeynep Toprak Deniz:
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS. CICC 2019: 1-4 - 2018
- [j4]Christopher J. Gonzalez
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53(1): 91-101 (2018) - 2017
- [c6]Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC 2017: 50-51 - [c5]Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis:
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ISSCC 2017: 444-445 - 2016
- [j3]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016) - 2015
- [j2]Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - [c4]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns:
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. ISSCC 2015: 1-3 - 2014
- [c3]Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. ISSCC 2014: 98-99 - 2011
- [j1]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. IEEE J. Solid State Circuits 46(1): 64-75 (2011) - 2010
- [c2]John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC 2010: 342-343
2000 – 2009
- 2008
- [c1]Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman:
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. CICC 2008: 431-434
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