default search action

combined dblp search
author search
venue search
publication search

ask others

"Designing Efficient Parallel Processing in 3D Standard-Chip Stacking ..."

Takeshi Ohkawa et al. (2017)

> Home

Details and statistics

DOI: 10.1109/MCSOC.2017.27

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/mcsoc/OhkawaOYKA17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mcsoc/OhkawaOYKA17
Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi:
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC 2017: 128-135

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.