default search action
Bulusu Anand
Anand Bulusu
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j20]Lomash Chandra Acharya, Arvind K. Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Neha Gupta, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu:
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4715-4725 (2024) - [j19]Dinesh Kushwaha
, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta
Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3166-3170 (2024) - [c51]Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta:
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS 2024: 184-188 - [c50]Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS 2024: 1-5 - [c49]Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta:
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED 2024: 1-6 - [c48]Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED 2024: 1-8 - [c47]Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu:
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED 2024: 1-8 - [c46]Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS 2024: 1-5 - [c45]Anmol Singla, Dinesh Kushwaha, Gulyawar Aman, Shubhradin Chakraborty, Abhishek Goel, Anand Bulusu, Sudeb Dasgupta:
An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture. NewCAS 2024: 233-237 - [c44]Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta:
Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS 2024: 243-247 - 2023
- [j18]Khoirom Johnson Singh
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. Microelectron. J. 142: 105981 (2023) - [j17]Lomash Chandra Acharya
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2657-2663 (2023) - [j16]Neeraj Mishra
Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3609-3613 (2023) - [c43]Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS 2023: 1-5 - [c42]Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu:
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS 2023: 100-104 - [c41]Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu:
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS 2023: 105-109 - [c40]Kartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu:
A Novel Low-Power Shift-Register Controller for Digital Low-Dropout Regulators. APCCAS 2023: 183-187 - [c39]Abhishek Acharya
Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight. ISCAS 2023: 1-5 - [c38]Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu:
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD 2023: 1-4 - [c37]Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta:
Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. VLSID 2023: 59-62 - [c36]Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID 2023: 359-364 - 2022
- [j15]Neeraj Mishra
Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4415-4428 (2022) - [j14]Neeraj Mishra
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 30-34 (2022) - [j13]Lalit Mohan Dani
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1557-1561 (2022) - [j12]Dinesh Kushwaha
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2311-2315 (2022) - [c35]Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu:
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 2022: 1-4 - [c34]Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI. IRPS 2022: 23-1 - [c33]Dinesh Kushwaha, Aditya Sharma
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS 2022: 1556-1560 - [c32]Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta:
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. ISCAS 2022: 3423-3427 - [c31]Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan:
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. VDAT 2022: 85-96 - [c30]Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta:
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID 2022: 292-296 - 2021
- [j11]Lalit Mohan Dani
An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2117-2127 (2021) - [c29]Ashutosh Yadav
Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm. ICM 2021: 166-169 - [c28]Khoirom Johnson Singh
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. ISCAS 2021: 1-5 - [c27]Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu:
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED 2021: 251-256 - [c26]Sarita Yadav, Nitanshu Chauhan, Archana Pandey
Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain. VDAT 2021: 1-5 - [c25]Shashank Banchhor, Nitanshu Chauhan, Aditya Doneria, Bulusu Anand:
Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect. VLSID 2021: 199-203 - 2020
- [j10]Neeraj Mishra
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals. IEEE Trans. Circuits Syst. 67-II(11): 2352-2356 (2020)
2010 – 2019
- 2019
- [j9]Chaudhry Indra Kumar
High performance energy efficient radiation hardened latch for low voltage applications. Integr. 66: 119-127 (2019) - [j8]Chaudhry Indra Kumar
An energy-efficient variation aware self-correcting latch. Microelectron. J. 84: 67-78 (2019) - [j7]Chaudhry Indra Kumar
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2170-2179 (2019) - [c24]Lalit Dani, Neeraj Mishra, Bulusu Anand:
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques. VLSID 2019: 41-45 - 2018
- [c23]Archana Pandey
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects. ISQED 2018: 189-195 - [c22]Arvind Kumar Sharma, Naushad Alam
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective. PRIME 2018: 57-60 - [c21]Chaudhry Indra Kumar, Anand Bulusu:
Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability. PRIME 2018: 101-104 - 2017
- [c20]Satish Maheshwaram
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. VDAT 2017: 239-248 - 2016
- [j6]Baljit Kaur
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53: 45-55 (2016) - [c19]Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram
Lateral silicon nanowire based standard cell design for higher performance. APCCAS 2016: 135-138 - [c18]Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu:
A novel energy-efficient self-correcting methodology employing INWE. SMACD 2016: 1-4 - [c17]Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand:
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis. SMACD 2016: 1-4 - [c16]Om. Prakash, Satish Maheshwaram
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. VDAT 2016: 1-6 - [c15]Archana Pandey
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSID 2016: 288-293 - 2015
- [c14]Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand:
Efficient static D-latch standard cell characterization using a novel setup time model. ISQED 2015: 371-378 - [c13]Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur
Timing model for two stage buffer and its application in ECSM characterization. VDAT 2015: 1-6 - [c12]Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT 2015: 1-6 - [c11]Sudeb Dasgupta, Bulusu Anand:
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. VLSID 2015: 12-13 - 2014
- [j5]Naushad Alam
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1714-1726 (2014) - [j4]Baljit Kaur
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3407-3415 (2014) - [c10]Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand:
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect. VDAT 2014: 1-2 - [c9]Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta:
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSID 2014: 411-414 - 2013
- [j3]Menka Yadav, Anand Bulusu, Sudeb Dasgupta:
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron. J. 44(12): 1251-1259 (2013) - [j2]Naushad Alam
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices. Microelectron. Reliab. 53(3): 379-385 (2013) - [j1]Naushad Alam
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design. Microelectron. Reliab. 53(5): 718-724 (2013) - [c8]Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand:
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED 2013: 665-669 - 2012
- [c7]Naushad Alam
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues. ISED 2012: 213-215 - [c6]Baljit Kaur
An accurate current source model for CMOS based combinational logic cell. ISQED 2012: 561-565 - [c5]Naushad Alam
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. ISQED 2012: 717-722 - [c4]Gunti Nagendra Babu, Brajesh Kumar Kaushik
Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects. VDAT 2012: 40-45 - [c3]Naushad Alam
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance. VDAT 2012: 357-359 - 2011
- [c2]Sandeep Miryala, Baljit Kaur
Efficient nanoscale VLSI standard cell library characterization using a novel delay model. ISQED 2011: 458-463 - [c1]Arnab Kumar Biswas
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. ISVLSI 2011: 108-113
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-12 21:01 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: