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"FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay."

Archana Pandey et al. (2016)

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DOI: 10.1109/VLSID.2016.15

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  dblp key:
  - conf/vlsid/PandeyKGDMB16
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PandeyKGDMB16
Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu:
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSID 2016: 288-293

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