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Vivek Asthana
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2020 – today
- 2022
- [c5]R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong:
5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. CICC 2022: 1-2 - 2020
- [c4]Vivek Asthana, M. Jagadesh Kumar, Ayush Kulshrestha, Munish Kumar, Saikat Kumar Banik, Shruti Aggarwal:
0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications. ISCAS 2020: 1-5
2010 – 2019
- 2014
- [c3]Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta:
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSID 2014: 411-414 - 2013
- [c2]Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy:
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. ESSCIRC 2013: 415-418 - [c1]Vivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy:
6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. ICICDT 2013: 89-92
Coauthor Index
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